module PC(
  input         clock,
  input         reset,
  input         io_ready_in,
  output        io_valid_out,
  output [31:0] io_npc,
  output [31:0] io_pc,
  input         io_NPC_Type,
  input  [31:0] io_pcImm,
  input         io_stall
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg [31:0] pcreg; // @[PC.scala 20:24]
  wire [31:0] _pcreg_T_1 = io_pc + 32'h4; // @[PC.scala 25:28]
  assign io_valid_out = io_ready_in & ~io_stall; // @[PC.scala 22:22]
  assign io_npc = io_NPC_Type ? _pcreg_T_1 : io_pcImm; // @[PC.scala 36:32 PC.scala 37:16 PC.scala 39:16]
  assign io_pc = pcreg; // @[PC.scala 41:11]
  always @(posedge clock) begin
    if (reset) begin // @[PC.scala 20:24]
      pcreg <= 32'h7ffffffc; // @[PC.scala 20:24]
    end else if (io_ready_in & ~io_stall) begin // @[PC.scala 22:35]
      if (io_NPC_Type) begin // @[PC.scala 24:37]
        pcreg <= _pcreg_T_1; // @[PC.scala 25:19]
      end else begin
        pcreg <= io_pcImm; // @[PC.scala 27:19]
      end
    end else begin
      pcreg <= io_pc; // @[PC.scala 32:15]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  pcreg = _RAND_0[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module IDReg(
  input         clock,
  input         reset,
  input  [31:0] io_pc_in,
  output [31:0] io_pc_out,
  input  [31:0] io_instr_in,
  output [31:0] io_instr_out,
  input         io_ready_in,
  output        io_ready_out,
  input         io_valid_in,
  output        io_valid_out,
  input         io_stallFromIF,
  input         io_stallFromEXE,
  input         io_stallFromMEM
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  reg [31:0] pcreg; // @[IDReg.scala 22:24]
  reg [31:0] instrreg; // @[IDReg.scala 23:27]
  wire  stall = io_stallFromEXE | io_stallFromMEM | io_stallFromIF; // @[IDReg.scala 25:49]
  assign io_pc_out = pcreg; // @[IDReg.scala 44:15]
  assign io_instr_out = instrreg; // @[IDReg.scala 45:18]
  assign io_ready_out = io_ready_in; // @[IDReg.scala 21:18]
  assign io_valid_out = io_stallFromIF | io_valid_in; // @[IDReg.scala 46:25 IDReg.scala 47:22 IDReg.scala 49:22]
  always @(posedge clock) begin
    if (reset) begin // @[IDReg.scala 22:24]
      pcreg <= 32'h0; // @[IDReg.scala 22:24]
    end else if (io_ready_in & ~stall) begin // @[IDReg.scala 26:32]
      pcreg <= io_pc_in; // @[IDReg.scala 28:15]
    end else begin
      pcreg <= io_pc_out;
    end
    if (reset) begin // @[IDReg.scala 23:27]
      instrreg <= 32'h0; // @[IDReg.scala 23:27]
    end else if (io_ready_in & ~stall) begin // @[IDReg.scala 26:32]
      instrreg <= io_instr_in; // @[IDReg.scala 29:18]
    end else if (io_ready_in & stall) begin // @[IDReg.scala 30:37]
      if (io_stallFromIF) begin // @[IDReg.scala 32:29]
        instrreg <= 32'h0; // @[IDReg.scala 35:22]
      end else begin
        instrreg <= io_instr_out; // @[IDReg.scala 38:22]
      end
    end else begin
      instrreg <= io_instr_out; // @[IDReg.scala 42:18]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  pcreg = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  instrreg = _RAND_1[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Decode(
  input  [31:0] io_instr_in,
  input  [31:0] io_pc_in,
  output        io_controlInfo_regwe,
  output [1:0]  io_controlInfo_wAddrSel,
  output [2:0]  io_controlInfo_ASel,
  output [2:0]  io_controlInfo_BSel,
  output [1:0]  io_controlInfo_immExtType,
  output [7:0]  io_controlInfo_op,
  output [31:0] io_instr_out,
  output [31:0] io_pc_out,
  output        io_ready_out,
  input         io_ready_in
);
  wire [31:0] _controlSignals_T = io_instr_in & 32'hfc0007ff; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_1 = 32'h20 == _controlSignals_T; // @[Lookup.scala 31:38]
  wire [31:0] _controlSignals_T_2 = io_instr_in & 32'hfc000000; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_3 = 32'h20000000 == _controlSignals_T_2; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_5 = 32'h21 == _controlSignals_T; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_7 = 32'h24000000 == _controlSignals_T_2; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_9 = 32'h22 == _controlSignals_T; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_11 = 32'h2a == _controlSignals_T; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_13 = 32'h70000002 == _controlSignals_T; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_15 = 32'h24 == _controlSignals_T; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_17 = 32'h30000000 == _controlSignals_T_2; // @[Lookup.scala 31:38]
  wire [31:0] _controlSignals_T_18 = io_instr_in & 32'hffe00000; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_19 = 32'h3c000000 == _controlSignals_T_18; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_21 = 32'h25 == _controlSignals_T; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_23 = 32'h34000000 == _controlSignals_T_2; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_25 = 32'h26 == _controlSignals_T; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_27 = 32'h38000000 == _controlSignals_T_2; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_29 = 32'h4 == _controlSignals_T; // @[Lookup.scala 31:38]
  wire [31:0] _controlSignals_T_30 = io_instr_in & 32'hffe0003f; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_31 = 32'h0 == _controlSignals_T_30; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_33 = 32'h7 == _controlSignals_T; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_35 = 32'h3 == _controlSignals_T_30; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_37 = 32'h6 == _controlSignals_T; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_39 = 32'h2 == _controlSignals_T_30; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_41 = 32'h10000000 == _controlSignals_T_2; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_43 = 32'h14000000 == _controlSignals_T_2; // @[Lookup.scala 31:38]
  wire [31:0] _controlSignals_T_44 = io_instr_in & 32'hfc1f0000; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_45 = 32'h4010000 == _controlSignals_T_44; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_47 = 32'h1c000000 == _controlSignals_T_44; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_49 = 32'h18000000 == _controlSignals_T_44; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_51 = 32'h4000000 == _controlSignals_T_44; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_53 = 32'h8000000 == _controlSignals_T_2; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_55 = 32'hc000000 == _controlSignals_T_2; // @[Lookup.scala 31:38]
  wire [31:0] _controlSignals_T_56 = io_instr_in & 32'hfc1fffff; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_57 = 32'h8 == _controlSignals_T_56; // @[Lookup.scala 31:38]
  wire [31:0] _controlSignals_T_58 = io_instr_in & 32'hfc1f07ff; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_59 = 32'h9 == _controlSignals_T_58; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_61 = 32'h80000000 == _controlSignals_T_2; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_63 = 32'h8c000000 == _controlSignals_T_2; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_65 = 32'ha0000000 == _controlSignals_T_2; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_67 = 32'hac000000 == _controlSignals_T_2; // @[Lookup.scala 31:38]
  wire  _controlSignals_T_106 = _controlSignals_T_57 ? 1'h0 : _controlSignals_T_59 | (_controlSignals_T_61 |
    _controlSignals_T_63); // @[Lookup.scala 33:37]
  wire  _controlSignals_T_108 = _controlSignals_T_53 ? 1'h0 : _controlSignals_T_55 | _controlSignals_T_106; // @[Lookup.scala 33:37]
  wire  _controlSignals_T_109 = _controlSignals_T_51 ? 1'h0 : _controlSignals_T_108; // @[Lookup.scala 33:37]
  wire  _controlSignals_T_110 = _controlSignals_T_49 ? 1'h0 : _controlSignals_T_109; // @[Lookup.scala 33:37]
  wire  _controlSignals_T_111 = _controlSignals_T_47 ? 1'h0 : _controlSignals_T_110; // @[Lookup.scala 33:37]
  wire  _controlSignals_T_112 = _controlSignals_T_45 ? 1'h0 : _controlSignals_T_111; // @[Lookup.scala 33:37]
  wire  _controlSignals_T_113 = _controlSignals_T_43 ? 1'h0 : _controlSignals_T_112; // @[Lookup.scala 33:37]
  wire  _controlSignals_T_114 = _controlSignals_T_41 ? 1'h0 : _controlSignals_T_113; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_136 = _controlSignals_T_63 ? 2'h2 : 2'h0; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_137 = _controlSignals_T_61 ? 2'h2 : _controlSignals_T_136; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_138 = _controlSignals_T_59 ? 2'h1 : _controlSignals_T_137; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_139 = _controlSignals_T_57 ? 2'h0 : _controlSignals_T_138; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_140 = _controlSignals_T_55 ? 2'h3 : _controlSignals_T_139; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_141 = _controlSignals_T_53 ? 2'h0 : _controlSignals_T_140; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_142 = _controlSignals_T_51 ? 2'h0 : _controlSignals_T_141; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_143 = _controlSignals_T_49 ? 2'h0 : _controlSignals_T_142; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_144 = _controlSignals_T_47 ? 2'h0 : _controlSignals_T_143; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_145 = _controlSignals_T_45 ? 2'h0 : _controlSignals_T_144; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_146 = _controlSignals_T_43 ? 2'h0 : _controlSignals_T_145; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_147 = _controlSignals_T_41 ? 2'h0 : _controlSignals_T_146; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_148 = _controlSignals_T_39 ? 2'h1 : _controlSignals_T_147; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_149 = _controlSignals_T_37 ? 2'h1 : _controlSignals_T_148; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_150 = _controlSignals_T_35 ? 2'h1 : _controlSignals_T_149; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_151 = _controlSignals_T_33 ? 2'h1 : _controlSignals_T_150; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_152 = _controlSignals_T_31 ? 2'h1 : _controlSignals_T_151; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_153 = _controlSignals_T_29 ? 2'h1 : _controlSignals_T_152; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_154 = _controlSignals_T_27 ? 2'h2 : _controlSignals_T_153; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_155 = _controlSignals_T_25 ? 2'h1 : _controlSignals_T_154; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_156 = _controlSignals_T_23 ? 2'h2 : _controlSignals_T_155; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_157 = _controlSignals_T_21 ? 2'h1 : _controlSignals_T_156; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_158 = _controlSignals_T_19 ? 2'h2 : _controlSignals_T_157; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_159 = _controlSignals_T_17 ? 2'h2 : _controlSignals_T_158; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_160 = _controlSignals_T_15 ? 2'h1 : _controlSignals_T_159; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_161 = _controlSignals_T_13 ? 2'h1 : _controlSignals_T_160; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_162 = _controlSignals_T_11 ? 2'h1 : _controlSignals_T_161; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_163 = _controlSignals_T_9 ? 2'h1 : _controlSignals_T_162; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_164 = _controlSignals_T_7 ? 2'h2 : _controlSignals_T_163; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_165 = _controlSignals_T_5 ? 2'h1 : _controlSignals_T_164; // @[Lookup.scala 33:37]
  wire [1:0] _controlSignals_T_166 = _controlSignals_T_3 ? 2'h2 : _controlSignals_T_165; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_167 = _controlSignals_T_67 ? 3'h7 : 3'h0; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_168 = _controlSignals_T_65 ? 3'h7 : _controlSignals_T_167; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_169 = _controlSignals_T_63 ? 3'h7 : _controlSignals_T_168; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_170 = _controlSignals_T_61 ? 3'h7 : _controlSignals_T_169; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_171 = _controlSignals_T_59 ? 3'h4 : _controlSignals_T_170; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_172 = _controlSignals_T_57 ? 3'h0 : _controlSignals_T_171; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_173 = _controlSignals_T_55 ? 3'h4 : _controlSignals_T_172; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_174 = _controlSignals_T_53 ? 3'h0 : _controlSignals_T_173; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_175 = _controlSignals_T_51 ? 3'h0 : _controlSignals_T_174; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_176 = _controlSignals_T_49 ? 3'h0 : _controlSignals_T_175; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_177 = _controlSignals_T_47 ? 3'h0 : _controlSignals_T_176; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_178 = _controlSignals_T_45 ? 3'h0 : _controlSignals_T_177; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_179 = _controlSignals_T_43 ? 3'h0 : _controlSignals_T_178; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_180 = _controlSignals_T_41 ? 3'h0 : _controlSignals_T_179; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_181 = _controlSignals_T_39 ? 3'h6 : _controlSignals_T_180; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_182 = _controlSignals_T_37 ? 3'h0 : _controlSignals_T_181; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_183 = _controlSignals_T_35 ? 3'h6 : _controlSignals_T_182; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_184 = _controlSignals_T_33 ? 3'h0 : _controlSignals_T_183; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_185 = _controlSignals_T_31 ? 3'h6 : _controlSignals_T_184; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_186 = _controlSignals_T_29 ? 3'h0 : _controlSignals_T_185; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_187 = _controlSignals_T_27 ? 3'h0 : _controlSignals_T_186; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_188 = _controlSignals_T_25 ? 3'h0 : _controlSignals_T_187; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_189 = _controlSignals_T_23 ? 3'h0 : _controlSignals_T_188; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_190 = _controlSignals_T_21 ? 3'h0 : _controlSignals_T_189; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_191 = _controlSignals_T_19 ? 3'h0 : _controlSignals_T_190; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_192 = _controlSignals_T_17 ? 3'h0 : _controlSignals_T_191; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_193 = _controlSignals_T_15 ? 3'h0 : _controlSignals_T_192; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_194 = _controlSignals_T_13 ? 3'h0 : _controlSignals_T_193; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_195 = _controlSignals_T_11 ? 3'h0 : _controlSignals_T_194; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_196 = _controlSignals_T_9 ? 3'h0 : _controlSignals_T_195; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_197 = _controlSignals_T_7 ? 3'h0 : _controlSignals_T_196; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_198 = _controlSignals_T_5 ? 3'h0 : _controlSignals_T_197; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_199 = _controlSignals_T_3 ? 3'h0 : _controlSignals_T_198; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_204 = _controlSignals_T_59 ? 3'h5 : 3'h1; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_205 = _controlSignals_T_57 ? 3'h5 : _controlSignals_T_204; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_206 = _controlSignals_T_55 ? 3'h5 : _controlSignals_T_205; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_207 = _controlSignals_T_53 ? 3'h1 : _controlSignals_T_206; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_208 = _controlSignals_T_51 ? 3'h1 : _controlSignals_T_207; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_209 = _controlSignals_T_49 ? 3'h1 : _controlSignals_T_208; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_210 = _controlSignals_T_47 ? 3'h1 : _controlSignals_T_209; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_211 = _controlSignals_T_45 ? 3'h1 : _controlSignals_T_210; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_212 = _controlSignals_T_43 ? 3'h1 : _controlSignals_T_211; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_213 = _controlSignals_T_41 ? 3'h1 : _controlSignals_T_212; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_214 = _controlSignals_T_39 ? 3'h1 : _controlSignals_T_213; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_215 = _controlSignals_T_37 ? 3'h1 : _controlSignals_T_214; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_216 = _controlSignals_T_35 ? 3'h1 : _controlSignals_T_215; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_217 = _controlSignals_T_33 ? 3'h1 : _controlSignals_T_216; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_218 = _controlSignals_T_31 ? 3'h1 : _controlSignals_T_217; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_219 = _controlSignals_T_29 ? 3'h1 : _controlSignals_T_218; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_220 = _controlSignals_T_27 ? 3'h3 : _controlSignals_T_219; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_221 = _controlSignals_T_25 ? 3'h1 : _controlSignals_T_220; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_222 = _controlSignals_T_23 ? 3'h3 : _controlSignals_T_221; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_223 = _controlSignals_T_21 ? 3'h1 : _controlSignals_T_222; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_224 = _controlSignals_T_19 ? 3'h3 : _controlSignals_T_223; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_225 = _controlSignals_T_17 ? 3'h3 : _controlSignals_T_224; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_226 = _controlSignals_T_15 ? 3'h1 : _controlSignals_T_225; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_227 = _controlSignals_T_13 ? 3'h1 : _controlSignals_T_226; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_228 = _controlSignals_T_11 ? 3'h1 : _controlSignals_T_227; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_229 = _controlSignals_T_9 ? 3'h1 : _controlSignals_T_228; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_230 = _controlSignals_T_7 ? 3'h3 : _controlSignals_T_229; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_231 = _controlSignals_T_5 ? 3'h1 : _controlSignals_T_230; // @[Lookup.scala 33:37]
  wire [2:0] _controlSignals_T_232 = _controlSignals_T_3 ? 3'h3 : _controlSignals_T_231; // @[Lookup.scala 33:37]
  wire  _controlSignals_T_264 = _controlSignals_T_5 ? 1'h0 : _controlSignals_T_7; // @[Lookup.scala 33:37]
  wire  controlSignals_5 = _controlSignals_T_1 | (_controlSignals_T_3 | _controlSignals_T_264); // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_266 = _controlSignals_T_67 ? 5'h1a : 5'h0; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_267 = _controlSignals_T_65 ? 5'h19 : _controlSignals_T_266; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_268 = _controlSignals_T_63 ? 5'h18 : _controlSignals_T_267; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_269 = _controlSignals_T_61 ? 5'h17 : _controlSignals_T_268; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_270 = _controlSignals_T_59 ? 5'h15 : _controlSignals_T_269; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_271 = _controlSignals_T_57 ? 5'h16 : _controlSignals_T_270; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_272 = _controlSignals_T_55 ? 5'h14 : _controlSignals_T_271; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_273 = _controlSignals_T_53 ? 5'h13 : _controlSignals_T_272; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_274 = _controlSignals_T_51 ? 5'h12 : _controlSignals_T_273; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_275 = _controlSignals_T_49 ? 5'h11 : _controlSignals_T_274; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_276 = _controlSignals_T_47 ? 5'h10 : _controlSignals_T_275; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_277 = _controlSignals_T_45 ? 5'hf : _controlSignals_T_276; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_278 = _controlSignals_T_43 ? 5'he : _controlSignals_T_277; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_279 = _controlSignals_T_41 ? 5'hd : _controlSignals_T_278; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_280 = _controlSignals_T_39 ? 5'hc : _controlSignals_T_279; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_281 = _controlSignals_T_37 ? 5'hc : _controlSignals_T_280; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_282 = _controlSignals_T_35 ? 5'hb : _controlSignals_T_281; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_283 = _controlSignals_T_33 ? 5'hb : _controlSignals_T_282; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_284 = _controlSignals_T_31 ? 5'ha : _controlSignals_T_283; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_285 = _controlSignals_T_29 ? 5'ha : _controlSignals_T_284; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_286 = _controlSignals_T_27 ? 5'h9 : _controlSignals_T_285; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_287 = _controlSignals_T_25 ? 5'h9 : _controlSignals_T_286; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_288 = _controlSignals_T_23 ? 5'h8 : _controlSignals_T_287; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_289 = _controlSignals_T_21 ? 5'h8 : _controlSignals_T_288; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_290 = _controlSignals_T_19 ? 5'h7 : _controlSignals_T_289; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_291 = _controlSignals_T_17 ? 5'h6 : _controlSignals_T_290; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_292 = _controlSignals_T_15 ? 5'h6 : _controlSignals_T_291; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_293 = _controlSignals_T_13 ? 5'h5 : _controlSignals_T_292; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_294 = _controlSignals_T_11 ? 5'h4 : _controlSignals_T_293; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_295 = _controlSignals_T_9 ? 5'h3 : _controlSignals_T_294; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_296 = _controlSignals_T_7 ? 5'h2 : _controlSignals_T_295; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_297 = _controlSignals_T_5 ? 5'h2 : _controlSignals_T_296; // @[Lookup.scala 33:37]
  wire [4:0] _controlSignals_T_298 = _controlSignals_T_3 ? 5'h1 : _controlSignals_T_297; // @[Lookup.scala 33:37]
  wire [4:0] controlSignals_6 = _controlSignals_T_1 ? 5'h1 : _controlSignals_T_298; // @[Lookup.scala 33:37]
  assign io_controlInfo_regwe = _controlSignals_T_1 | (_controlSignals_T_3 | (_controlSignals_T_5 | (_controlSignals_T_7
     | (_controlSignals_T_9 | (_controlSignals_T_11 | (_controlSignals_T_13 | (_controlSignals_T_15 | (
    _controlSignals_T_17 | (_controlSignals_T_19 | (_controlSignals_T_21 | (_controlSignals_T_23 | (_controlSignals_T_25
     | (_controlSignals_T_27 | (_controlSignals_T_29 | (_controlSignals_T_31 | (_controlSignals_T_33 | (
    _controlSignals_T_35 | (_controlSignals_T_37 | (_controlSignals_T_39 | _controlSignals_T_114))))))))))))))))))); // @[Lookup.scala 33:37]
  assign io_controlInfo_wAddrSel = _controlSignals_T_1 ? 2'h1 : _controlSignals_T_166; // @[Lookup.scala 33:37]
  assign io_controlInfo_ASel = _controlSignals_T_1 ? 3'h0 : _controlSignals_T_199; // @[Lookup.scala 33:37]
  assign io_controlInfo_BSel = _controlSignals_T_1 ? 3'h1 : _controlSignals_T_232; // @[Lookup.scala 33:37]
  assign io_controlInfo_immExtType = {{1'd0}, controlSignals_5}; // @[Lookup.scala 33:37]
  assign io_controlInfo_op = {{3'd0}, controlSignals_6}; // @[Lookup.scala 33:37]
  assign io_instr_out = io_instr_in; // @[Decode.scala 19:18]
  assign io_pc_out = io_pc_in; // @[Decode.scala 20:15]
  assign io_ready_out = io_ready_in; // @[Decode.scala 77:18]
endmodule
module Control(
  input         io_controlInfo_regwe,
  input  [1:0]  io_controlInfo_wAddrSel,
  input  [2:0]  io_controlInfo_ASel,
  input  [2:0]  io_controlInfo_BSel,
  input  [1:0]  io_controlInfo_immExtType,
  input  [7:0]  io_controlInfo_op,
  input  [31:0] io_instr,
  input  [31:0] io_pc,
  input  [31:0] io_rsData,
  input  [31:0] io_rtData,
  input  [4:0]  io_bypassFromExe_regAddr,
  input  [31:0] io_bypassFromExe_regData,
  input  [4:0]  io_bypassFromMem_regAddr,
  input  [31:0] io_bypassFromMem_regData,
  output [4:0]  io_rsAddr,
  output [4:0]  io_rtAddr,
  output        io_NPC_Type,
  output [31:0] io_NextPC,
  output [31:0] io_exeInfo_OperA,
  output [31:0] io_exeInfo_OperB,
  output        io_exeInfo_regwe,
  output [4:0]  io_exeInfo_wAddr,
  output [7:0]  io_exeInfo_op,
  output        io_exeInfo_AFromReg,
  output        io_exeInfo_BFromReg,
  output [4:0]  io_exeInfo_ARegAddr,
  output [4:0]  io_exeInfo_BRegAddr,
  input         io_ready_in,
  output        io_ready_out,
  input         io_valid_in,
  output        io_valid_out,
  input         io_isLBandLW,
  input  [4:0]  io_wregAddr,
  output        io_stallFromID
);
  wire [4:0] rsAddr = io_instr[25:21]; // @[Control.scala 51:23]
  wire [4:0] rtAddr = io_instr[20:16]; // @[Control.scala 52:23]
  wire [4:0] rdAddr = io_instr[15:11]; // @[Control.scala 53:23]
  wire [4:0] sa = io_instr[10:6]; // @[Control.scala 54:19]
  wire [15:0] imm = io_instr[15:0]; // @[Control.scala 55:20]
  wire [25:0] instrAddrImm = io_instr[25:0]; // @[Control.scala 57:29]
  wire [31:0] _immAfterExt_T = {16'hffff,imm}; // @[Cat.scala 30:58]
  wire [31:0] _immAfterExt_T_1 = {16'h0,imm}; // @[Cat.scala 30:58]
  wire [31:0] immAfterExt = io_controlInfo_immExtType == 2'h1 & imm[15] ? _immAfterExt_T : _immAfterExt_T_1; // @[Control.scala 60:68 Control.scala 61:21 Control.scala 63:21]
  wire  _T_4 = io_bypassFromExe_regAddr != rsAddr; // @[Control.scala 68:35]
  wire  _T_5 = io_bypassFromMem_regAddr != rsAddr; // @[Control.scala 68:74]
  wire  _T_8 = rsAddr != 5'h0; // @[Control.scala 70:62]
  wire  _T_9 = io_bypassFromExe_regAddr == rsAddr & rsAddr != 5'h0; // @[Control.scala 70:52]
  wire  _T_10 = io_bypassFromMem_regAddr == rsAddr; // @[Control.scala 70:98]
  wire [31:0] _GEN_1 = _T_4 & _T_8 & _T_10 ? io_bypassFromMem_regData : io_rsData; // @[Control.scala 74:109 Control.scala 75:20 Control.scala 77:20]
  wire [31:0] _GEN_2 = _T_9 & _T_5 ? io_bypassFromExe_regData : _GEN_1; // @[Control.scala 72:109 Control.scala 73:20]
  wire [31:0] _GEN_3 = io_bypassFromExe_regAddr == rsAddr & rsAddr != 5'h0 & io_bypassFromMem_regAddr == rsAddr ?
    io_bypassFromExe_regData : _GEN_2; // @[Control.scala 70:109 Control.scala 71:20]
  wire [31:0] trueRSData = io_bypassFromExe_regAddr != rsAddr & io_bypassFromMem_regAddr != rsAddr ? io_rsData : _GEN_3; // @[Control.scala 68:85 Control.scala 69:20]
  wire  _T_22 = io_bypassFromExe_regAddr != rtAddr; // @[Control.scala 79:35]
  wire  _T_23 = io_bypassFromMem_regAddr != rtAddr; // @[Control.scala 79:74]
  wire  _T_26 = rtAddr != 5'h0; // @[Control.scala 81:62]
  wire  _T_27 = io_bypassFromExe_regAddr == rtAddr & rtAddr != 5'h0; // @[Control.scala 81:52]
  wire  _T_28 = io_bypassFromMem_regAddr == rtAddr; // @[Control.scala 81:98]
  wire [31:0] _GEN_5 = _T_22 & _T_26 & _T_28 ? io_bypassFromMem_regData : io_rtData; // @[Control.scala 85:109 Control.scala 86:20 Control.scala 88:20]
  wire [31:0] _GEN_6 = _T_27 & _T_23 ? io_bypassFromExe_regData : _GEN_5; // @[Control.scala 83:109 Control.scala 84:20]
  wire [31:0] _GEN_7 = io_bypassFromExe_regAddr == rtAddr & rtAddr != 5'h0 & io_bypassFromMem_regAddr == rtAddr ?
    io_bypassFromExe_regData : _GEN_6; // @[Control.scala 81:109 Control.scala 82:20]
  wire [31:0] trueRTData = io_bypassFromExe_regAddr != rtAddr & io_bypassFromMem_regAddr != rtAddr ? io_rtData : _GEN_7; // @[Control.scala 79:85 Control.scala 80:20]
  wire [32:0] signRSData = {1'h0,trueRSData}; // @[Control.scala 94:50]
  wire [15:0] _memaddr_T = io_instr[15:0]; // @[Control.scala 96:43]
  wire [32:0] _GEN_61 = {{17{_memaddr_T[15]}},_memaddr_T}; // @[Control.scala 96:28]
  wire [32:0] _memaddr_T_4 = $signed(signRSData) + $signed(_GEN_61); // @[Control.scala 96:53]
  wire [31:0] memaddr = _memaddr_T_4[31:0]; // @[Control.scala 96:55]
  wire  _T_44 = ~memaddr[22]; // @[Control.scala 98:26]
  wire [31:0] _io_exeInfo_OperA_T_1 = io_pc + 32'h8; // @[Control.scala 108:35]
  wire [31:0] _io_exeInfo_OperA_T_2 = {27'h0,sa}; // @[Cat.scala 30:58]
  wire [31:0] _GEN_11 = io_controlInfo_ASel == 3'h7 ? memaddr : trueRSData; // @[Control.scala 115:51 Control.scala 116:26 Control.scala 120:26]
  wire  _GEN_12 = io_controlInfo_ASel == 3'h7 ? 1'h0 : 1'h1; // @[Control.scala 115:51 Control.scala 117:29 Control.scala 121:29]
  wire [4:0] _GEN_13 = io_controlInfo_ASel == 3'h7 ? 5'h0 : rsAddr; // @[Control.scala 115:51 Control.scala 118:29 Control.scala 122:29]
  wire [31:0] _GEN_14 = io_controlInfo_ASel == 3'h6 ? _io_exeInfo_OperA_T_2 : _GEN_11; // @[Control.scala 111:47 Control.scala 112:26]
  wire  _GEN_15 = io_controlInfo_ASel == 3'h6 ? 1'h0 : _GEN_12; // @[Control.scala 111:47 Control.scala 113:29]
  wire [4:0] _GEN_16 = io_controlInfo_ASel == 3'h6 ? 5'h0 : _GEN_13; // @[Control.scala 111:47 Control.scala 114:29]
  wire [31:0] _GEN_20 = io_controlInfo_BSel == 3'h3 ? immAfterExt : trueRTData; // @[Control.scala 128:48 Control.scala 129:26 Control.scala 133:26]
  wire  _GEN_21 = io_controlInfo_BSel == 3'h3 ? 1'h0 : 1'h1; // @[Control.scala 128:48 Control.scala 130:29 Control.scala 134:29]
  wire [4:0] _GEN_22 = io_controlInfo_BSel == 3'h3 ? 5'h0 : rtAddr; // @[Control.scala 128:48 Control.scala 131:29 Control.scala 135:29]
  wire [4:0] _GEN_26 = io_controlInfo_wAddrSel == 2'h2 ? rtAddr : 5'h0; // @[Control.scala 143:53 Control.scala 144:26 Control.scala 146:26]
  wire [4:0] _GEN_27 = io_controlInfo_wAddrSel == 2'h1 ? rdAddr : _GEN_26; // @[Control.scala 141:53 Control.scala 142:26]
  wire [17:0] offsetAfterExt = {$signed(_memaddr_T), 2'h0}; // @[Control.scala 154:39]
  wire [31:0] _signpc_T_3 = $signed(io_pc) + 32'sh4; // @[Control.scala 157:29]
  wire  _T_72 = 8'hd == io_controlInfo_op | 8'he == io_controlInfo_op | 8'hf == io_controlInfo_op | 8'h10 ==
    io_controlInfo_op | 8'h11 == io_controlInfo_op | 8'h12 == io_controlInfo_op | 8'h13 == io_controlInfo_op | 8'h14 ==
    io_controlInfo_op | 8'h15 == io_controlInfo_op | 8'h16 == io_controlInfo_op; // @[CommonConfig.scala 119:90]
  wire [32:0] signpc = {{1{_signpc_T_3[31]}},_signpc_T_3}; // @[Control.scala 156:22 Control.scala 157:12]
  wire [32:0] _GEN_63 = {{15{offsetAfterExt[17]}},offsetAfterExt}; // @[Control.scala 165:32]
  wire [32:0] _npc_T_3 = $signed(signpc) + $signed(_GEN_63); // @[Control.scala 165:56]
  wire [32:0] _GEN_29 = io_exeInfo_OperA == io_exeInfo_OperB ? _npc_T_3 : 33'h0; // @[Control.scala 164:57 Control.scala 165:21 Control.scala 169:21]
  wire  _GEN_30 = io_exeInfo_OperA == io_exeInfo_OperB ? 1'h0 : 1'h1; // @[Control.scala 164:57 Control.scala 166:29 Control.scala 168:29]
  wire [32:0] _GEN_31 = io_exeInfo_OperA != io_exeInfo_OperB ? _npc_T_3 : 33'h0; // @[Control.scala 172:57 Control.scala 173:21 Control.scala 176:21]
  wire  _GEN_32 = io_exeInfo_OperA != io_exeInfo_OperB ? 1'h0 : 1'h1; // @[Control.scala 172:57 Control.scala 174:29 Control.scala 177:29]
  wire  _T_80 = ~io_exeInfo_OperA[31]; // @[Control.scala 180:39]
  wire [32:0] _GEN_33 = ~io_exeInfo_OperA[31] ? _npc_T_3 : 33'h0; // @[Control.scala 180:47 Control.scala 181:21 Control.scala 184:21]
  wire  _GEN_34 = ~io_exeInfo_OperA[31] ? 1'h0 : 1'h1; // @[Control.scala 180:47 Control.scala 182:29 Control.scala 185:29]
  wire [32:0] _GEN_35 = _T_80 & io_exeInfo_OperA != 32'h0 ? _npc_T_3 : 33'h0; // @[Control.scala 188:76 Control.scala 189:21 Control.scala 192:21]
  wire  _GEN_36 = _T_80 & io_exeInfo_OperA != 32'h0 ? 1'h0 : 1'h1; // @[Control.scala 188:76 Control.scala 190:29 Control.scala 193:29]
  wire [32:0] _GEN_37 = io_exeInfo_OperA[31] | io_exeInfo_OperA == 32'h0 ? _npc_T_3 : 33'h0; // @[Control.scala 196:75 Control.scala 197:21 Control.scala 200:21]
  wire  _GEN_38 = io_exeInfo_OperA[31] | io_exeInfo_OperA == 32'h0 ? 1'h0 : 1'h1; // @[Control.scala 196:75 Control.scala 198:29 Control.scala 201:29]
  wire [3:0] npc_hi = io_pc[31:28]; // @[Control.scala 204:29]
  wire [29:0] _npc_T_20 = {npc_hi,instrAddrImm}; // @[Cat.scala 30:58]
  wire [31:0] _npc_T_21 = {_npc_T_20, 2'h0}; // @[Control.scala 204:51]
  wire [32:0] _GEN_39 = io_exeInfo_OperA[31] ? _npc_T_3 : 33'h0; // @[Control.scala 210:47 Control.scala 211:21 Control.scala 214:21]
  wire  _GEN_40 = io_exeInfo_OperA[31] ? 1'h0 : 1'h1; // @[Control.scala 210:47 Control.scala 212:29 Control.scala 215:29]
  wire [32:0] _GEN_41 = io_controlInfo_op == 8'h15 | io_controlInfo_op == 8'h16 ? {{1'd0}, trueRSData} : _GEN_39; // @[Control.scala 206:81 Control.scala 207:17]
  wire  _GEN_42 = io_controlInfo_op == 8'h15 | io_controlInfo_op == 8'h16 ? 1'h0 : _GEN_40; // @[Control.scala 206:81 Control.scala 208:25]
  wire [32:0] _GEN_43 = io_controlInfo_op == 8'h13 | io_controlInfo_op == 8'h14 ? {{1'd0}, _npc_T_21} : _GEN_41; // @[Control.scala 203:80 Control.scala 204:17]
  wire  _GEN_44 = io_controlInfo_op == 8'h13 | io_controlInfo_op == 8'h14 ? 1'h0 : _GEN_42; // @[Control.scala 203:80 Control.scala 205:25]
  wire [32:0] _GEN_45 = io_controlInfo_op == 8'h11 ? _GEN_37 : _GEN_43; // @[Control.scala 195:51]
  wire  _GEN_46 = io_controlInfo_op == 8'h11 ? _GEN_38 : _GEN_44; // @[Control.scala 195:51]
  wire [32:0] _GEN_47 = io_controlInfo_op == 8'h10 ? _GEN_35 : _GEN_45; // @[Control.scala 187:50]
  wire  _GEN_48 = io_controlInfo_op == 8'h10 ? _GEN_36 : _GEN_46; // @[Control.scala 187:50]
  wire [32:0] _GEN_49 = io_controlInfo_op == 8'hf ? _GEN_33 : _GEN_47; // @[Control.scala 179:50]
  wire  _GEN_50 = io_controlInfo_op == 8'hf ? _GEN_34 : _GEN_48; // @[Control.scala 179:50]
  wire [32:0] _GEN_51 = io_controlInfo_op == 8'he ? _GEN_31 : _GEN_49; // @[Control.scala 171:50]
  wire  _GEN_52 = io_controlInfo_op == 8'he ? _GEN_32 : _GEN_50; // @[Control.scala 171:50]
  wire [32:0] _GEN_53 = io_controlInfo_op == 8'hd ? _GEN_29 : _GEN_51; // @[Control.scala 163:43]
  wire  _GEN_54 = io_controlInfo_op == 8'hd ? _GEN_30 : _GEN_52; // @[Control.scala 163:43]
  wire [32:0] _GEN_55 = ~_T_72 ? 33'h0 : _GEN_53; // @[Control.scala 159:56 Control.scala 160:13]
  wire  _GEN_57 = io_wregAddr == io_rsAddr | io_wregAddr == io_rtAddr ? 1'h0 : io_ready_in; // @[Control.scala 223:69 Control.scala 224:26 Control.scala 227:26]
  wire  _GEN_58 = io_wregAddr == io_rsAddr | io_wregAddr == io_rtAddr ? 1'h0 : io_valid_in; // @[Control.scala 223:69 Control.scala 225:26 Control.scala 228:26]
  assign io_rsAddr = io_instr[25:21]; // @[Control.scala 51:23]
  assign io_rtAddr = io_instr[20:16]; // @[Control.scala 52:23]
  assign io_NPC_Type = ~_T_72 | _GEN_54; // @[Control.scala 159:56 Control.scala 161:21]
  assign io_NextPC = _GEN_55[31:0]; // @[Control.scala 155:19]
  assign io_exeInfo_OperA = io_controlInfo_ASel == 3'h4 ? _io_exeInfo_OperA_T_1 : _GEN_14; // @[Control.scala 107:46 Control.scala 108:26]
  assign io_exeInfo_OperB = io_controlInfo_BSel == 3'h5 ? 32'h0 : _GEN_20; // @[Control.scala 124:43 Control.scala 125:26]
  assign io_exeInfo_regwe = io_controlInfo_regwe; // @[Control.scala 138:22]
  assign io_exeInfo_wAddr = io_controlInfo_wAddrSel == 2'h3 ? 5'h1f : _GEN_27; // @[Control.scala 139:47 Control.scala 140:26]
  assign io_exeInfo_op = io_controlInfo_op; // @[Control.scala 148:19]
  assign io_exeInfo_AFromReg = io_controlInfo_ASel == 3'h4 ? 1'h0 : _GEN_15; // @[Control.scala 107:46 Control.scala 109:29]
  assign io_exeInfo_BFromReg = io_controlInfo_BSel == 3'h5 ? 1'h0 : _GEN_21; // @[Control.scala 124:43 Control.scala 126:29]
  assign io_exeInfo_ARegAddr = io_controlInfo_ASel == 3'h4 ? 5'h0 : _GEN_16; // @[Control.scala 107:46 Control.scala 110:29]
  assign io_exeInfo_BRegAddr = io_controlInfo_BSel == 3'h5 ? 5'h0 : _GEN_22; // @[Control.scala 124:43 Control.scala 127:29]
  assign io_ready_out = io_isLBandLW ? _GEN_57 : io_ready_in; // @[Control.scala 222:34 Control.scala 232:22]
  assign io_valid_out = io_isLBandLW ? _GEN_58 : io_valid_in; // @[Control.scala 222:34 Control.scala 233:22]
  assign io_stallFromID = (io_controlInfo_op == 8'h1a | io_controlInfo_op == 8'h19) & _T_44; // @[Control.scala 97:69 Control.scala 105:24]
endmodule
module EXEReg(
  input         clock,
  input         reset,
  input  [31:0] io_exeInfo_in_OperA,
  input  [31:0] io_exeInfo_in_OperB,
  input         io_exeInfo_in_regwe,
  input  [4:0]  io_exeInfo_in_wAddr,
  input  [7:0]  io_exeInfo_in_op,
  input         io_exeInfo_in_AFromReg,
  input         io_exeInfo_in_BFromReg,
  input  [4:0]  io_exeInfo_in_ARegAddr,
  input  [4:0]  io_exeInfo_in_BRegAddr,
  output [31:0] io_exeInfo_out_OperA,
  output [31:0] io_exeInfo_out_OperB,
  output        io_exeInfo_out_regwe,
  output [4:0]  io_exeInfo_out_wAddr,
  output [7:0]  io_exeInfo_out_op,
  output        io_exeInfo_out_AFromReg,
  output        io_exeInfo_out_BFromReg,
  output [4:0]  io_exeInfo_out_ARegAddr,
  output [4:0]  io_exeInfo_out_BRegAddr,
  input         io_valid_in,
  input         io_ready_in,
  output        io_ready_out
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
  reg [31:0] OperAtmp; // @[EXEReg.scala 18:27]
  reg [31:0] OperBtmp; // @[EXEReg.scala 19:27]
  reg  regwetmp; // @[EXEReg.scala 20:27]
  reg [4:0] wAddrtmp; // @[EXEReg.scala 21:27]
  reg [7:0] optmp; // @[EXEReg.scala 22:24]
  reg  AFromRegtmp; // @[EXEReg.scala 23:30]
  reg  BFromRegtmp; // @[EXEReg.scala 24:30]
  reg [4:0] ARegAddr; // @[EXEReg.scala 25:27]
  reg [4:0] BRegAddr; // @[EXEReg.scala 26:27]
  wire  _GEN_2 = ~io_ready_in & io_exeInfo_out_regwe; // @[EXEReg.scala 38:38 EXEReg.scala 42:18 EXEReg.scala 52:18]
  wire  _GEN_5 = ~io_ready_in & io_exeInfo_out_AFromReg; // @[EXEReg.scala 38:38 EXEReg.scala 45:21 EXEReg.scala 55:21]
  wire  _GEN_6 = ~io_ready_in & io_exeInfo_out_BFromReg; // @[EXEReg.scala 38:38 EXEReg.scala 46:21 EXEReg.scala 56:21]
  assign io_exeInfo_out_OperA = OperAtmp; // @[EXEReg.scala 60:26]
  assign io_exeInfo_out_OperB = OperBtmp; // @[EXEReg.scala 61:26]
  assign io_exeInfo_out_regwe = regwetmp; // @[EXEReg.scala 63:26]
  assign io_exeInfo_out_wAddr = wAddrtmp; // @[EXEReg.scala 64:26]
  assign io_exeInfo_out_op = optmp; // @[EXEReg.scala 62:23]
  assign io_exeInfo_out_AFromReg = AFromRegtmp; // @[EXEReg.scala 65:29]
  assign io_exeInfo_out_BFromReg = BFromRegtmp; // @[EXEReg.scala 66:29]
  assign io_exeInfo_out_ARegAddr = ARegAddr; // @[EXEReg.scala 67:29]
  assign io_exeInfo_out_BRegAddr = BRegAddr; // @[EXEReg.scala 68:29]
  assign io_ready_out = io_ready_in; // @[EXEReg.scala 17:18]
  always @(posedge clock) begin
    if (reset) begin // @[EXEReg.scala 18:27]
      OperAtmp <= 32'h0; // @[EXEReg.scala 18:27]
    end else if (io_valid_in & io_ready_in) begin // @[EXEReg.scala 28:37]
      OperAtmp <= io_exeInfo_in_OperA; // @[EXEReg.scala 29:18]
    end else if (~io_ready_in) begin // @[EXEReg.scala 38:38]
      OperAtmp <= io_exeInfo_out_OperA; // @[EXEReg.scala 40:18]
    end else begin
      OperAtmp <= 32'h0; // @[EXEReg.scala 50:18]
    end
    if (reset) begin // @[EXEReg.scala 19:27]
      OperBtmp <= 32'h0; // @[EXEReg.scala 19:27]
    end else if (io_valid_in & io_ready_in) begin // @[EXEReg.scala 28:37]
      OperBtmp <= io_exeInfo_in_OperB; // @[EXEReg.scala 30:18]
    end else if (~io_ready_in) begin // @[EXEReg.scala 38:38]
      OperBtmp <= io_exeInfo_out_OperB; // @[EXEReg.scala 41:18]
    end else begin
      OperBtmp <= 32'h0; // @[EXEReg.scala 51:18]
    end
    if (reset) begin // @[EXEReg.scala 20:27]
      regwetmp <= 1'h0; // @[EXEReg.scala 20:27]
    end else if (io_valid_in & io_ready_in) begin // @[EXEReg.scala 28:37]
      regwetmp <= io_exeInfo_in_regwe; // @[EXEReg.scala 31:18]
    end else begin
      regwetmp <= _GEN_2;
    end
    if (reset) begin // @[EXEReg.scala 21:27]
      wAddrtmp <= 5'h0; // @[EXEReg.scala 21:27]
    end else if (io_valid_in & io_ready_in) begin // @[EXEReg.scala 28:37]
      wAddrtmp <= io_exeInfo_in_wAddr; // @[EXEReg.scala 32:18]
    end else if (~io_ready_in) begin // @[EXEReg.scala 38:38]
      wAddrtmp <= io_exeInfo_out_wAddr; // @[EXEReg.scala 43:18]
    end else begin
      wAddrtmp <= 5'h0; // @[EXEReg.scala 53:18]
    end
    if (reset) begin // @[EXEReg.scala 22:24]
      optmp <= 8'h0; // @[EXEReg.scala 22:24]
    end else if (io_valid_in & io_ready_in) begin // @[EXEReg.scala 28:37]
      optmp <= io_exeInfo_in_op; // @[EXEReg.scala 33:15]
    end else if (~io_ready_in) begin // @[EXEReg.scala 38:38]
      optmp <= io_exeInfo_out_op; // @[EXEReg.scala 44:15]
    end else begin
      optmp <= 8'h0; // @[EXEReg.scala 54:15]
    end
    if (reset) begin // @[EXEReg.scala 23:30]
      AFromRegtmp <= 1'h0; // @[EXEReg.scala 23:30]
    end else if (io_valid_in & io_ready_in) begin // @[EXEReg.scala 28:37]
      AFromRegtmp <= io_exeInfo_in_AFromReg; // @[EXEReg.scala 34:21]
    end else begin
      AFromRegtmp <= _GEN_5;
    end
    if (reset) begin // @[EXEReg.scala 24:30]
      BFromRegtmp <= 1'h0; // @[EXEReg.scala 24:30]
    end else if (io_valid_in & io_ready_in) begin // @[EXEReg.scala 28:37]
      BFromRegtmp <= io_exeInfo_in_BFromReg; // @[EXEReg.scala 35:21]
    end else begin
      BFromRegtmp <= _GEN_6;
    end
    if (reset) begin // @[EXEReg.scala 25:27]
      ARegAddr <= 5'h0; // @[EXEReg.scala 25:27]
    end else if (io_valid_in & io_ready_in) begin // @[EXEReg.scala 28:37]
      ARegAddr <= io_exeInfo_in_ARegAddr; // @[EXEReg.scala 36:18]
    end else if (~io_ready_in) begin // @[EXEReg.scala 38:38]
      ARegAddr <= io_exeInfo_out_ARegAddr; // @[EXEReg.scala 47:18]
    end else begin
      ARegAddr <= 5'h0; // @[EXEReg.scala 57:18]
    end
    if (reset) begin // @[EXEReg.scala 26:27]
      BRegAddr <= 5'h0; // @[EXEReg.scala 26:27]
    end else if (io_valid_in & io_ready_in) begin // @[EXEReg.scala 28:37]
      BRegAddr <= io_exeInfo_in_BRegAddr; // @[EXEReg.scala 37:18]
    end else if (~io_ready_in) begin // @[EXEReg.scala 38:38]
      BRegAddr <= io_exeInfo_out_BRegAddr; // @[EXEReg.scala 48:18]
    end else begin
      BRegAddr <= 5'h0; // @[EXEReg.scala 58:18]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  OperAtmp = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  OperBtmp = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  regwetmp = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  wAddrtmp = _RAND_3[4:0];
  _RAND_4 = {1{`RANDOM}};
  optmp = _RAND_4[7:0];
  _RAND_5 = {1{`RANDOM}};
  AFromRegtmp = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  BFromRegtmp = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  ARegAddr = _RAND_7[4:0];
  _RAND_8 = {1{`RANDOM}};
  BRegAddr = _RAND_8[4:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module ALU(
  input         clock,
  input         reset,
  output        io_ready_out,
  output        io_valid_out,
  input  [31:0] io_exeInfo_OperA,
  input  [31:0] io_exeInfo_OperB,
  input         io_exeInfo_regwe,
  input  [4:0]  io_exeInfo_wAddr,
  input  [7:0]  io_exeInfo_op,
  input         io_exeInfo_AFromReg,
  input         io_exeInfo_BFromReg,
  input  [4:0]  io_exeInfo_ARegAddr,
  input  [4:0]  io_exeInfo_BRegAddr,
  output [2:0]  io_memInfo_memType,
  output [31:0] io_memInfo_memAddr,
  output        io_wbInfo_regwe,
  output [4:0]  io_wbInfo_regAddr,
  output [31:0] io_wbInfo_wData,
  output [4:0]  io_bypassFromExe_regAddr,
  output [31:0] io_bypassFromExe_regData,
  input  [4:0]  io_bypassFromMem2_regAddr,
  input  [31:0] io_bypassFromMem2_regData,
  output        io_isLBandLW,
  output [4:0]  io_wregAddr,
  output        io_stallFromEXE,
  output [31:0] io_addr,
  output        io_wr,
  output [1:0]  io_size,
  output [31:0] io_wdata,
  output [31:0] io_OpA,
  output [31:0] io_OpB,
  input  [31:0] io_mulans
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  wire  _T = io_bypassFromMem2_regAddr != 5'h0; // @[ALU.scala 44:36]
  wire [31:0] trueA = io_bypassFromMem2_regAddr != 5'h0 & io_exeInfo_AFromReg & io_exeInfo_ARegAddr ==
    io_bypassFromMem2_regAddr ? io_bypassFromMem2_regData : io_exeInfo_OperA; // @[ALU.scala 44:131 ALU.scala 45:15 ALU.scala 47:15]
  wire [31:0] trueB = _T & io_exeInfo_BFromReg & io_exeInfo_BRegAddr == io_bypassFromMem2_regAddr ?
    io_bypassFromMem2_regData : io_exeInfo_OperB; // @[ALU.scala 49:131 ALU.scala 50:15 ALU.scala 52:15]
  wire  signOperA_hi = trueA[31]; // @[ALU.scala 54:27]
  wire [32:0] signOperA = {signOperA_hi,trueA}; // @[Cat.scala 30:58]
  wire  signOperB_hi = trueB[31]; // @[ALU.scala 55:27]
  wire [32:0] signOperB = {signOperB_hi,trueB}; // @[Cat.scala 30:58]
  wire [32:0] addAns = signOperA + signOperB; // @[ALU.scala 56:25]
  wire [32:0] subAns = signOperA - signOperB; // @[ALU.scala 57:25]
  wire [31:0] _GEN_3 = addAns[32] != addAns[31] ? addAns[31:0] : addAns[31:0]; // @[ALU.scala 67:41 ALU.scala 69:22 ALU.scala 72:22]
  wire [31:0] _GEN_5 = subAns[32] != subAns[31] ? subAns[31:0] : subAns[31:0]; // @[ALU.scala 78:41 ALU.scala 80:22 ALU.scala 83:22]
  wire [31:0] _T_20 = io_bypassFromMem2_regAddr != 5'h0 & io_exeInfo_AFromReg & io_exeInfo_ARegAddr ==
    io_bypassFromMem2_regAddr ? io_bypassFromMem2_regData : io_exeInfo_OperA; // @[ALU.scala 87:26]
  wire [31:0] _T_21 = _T & io_exeInfo_BFromReg & io_exeInfo_BRegAddr == io_bypassFromMem2_regAddr ?
    io_bypassFromMem2_regData : io_exeInfo_OperB; // @[ALU.scala 87:43]
  wire  _T_22 = $signed(_T_20) < $signed(_T_21); // @[ALU.scala 87:29]
  wire  _T_23 = io_exeInfo_op == 8'h5; // @[ALU.scala 92:30]
  wire [31:0] _wdatatmp_T_5 = trueA & trueB; // @[ALU.scala 98:27]
  wire [15:0] wdatatmp_hi = trueB[15:0]; // @[ALU.scala 101:30]
  wire [31:0] _wdatatmp_T_6 = {wdatatmp_hi,16'h0}; // @[Cat.scala 30:58]
  wire [31:0] _wdatatmp_T_7 = trueA | trueB; // @[ALU.scala 104:27]
  wire [31:0] _wdatatmp_T_8 = trueA ^ trueB; // @[ALU.scala 107:27]
  wire [94:0] _GEN_67 = {{63'd0}, trueB}; // @[ALU.scala 110:27]
  wire [94:0] _wdatatmp_T_10 = _GEN_67 << trueA[5:0]; // @[ALU.scala 110:27]
  wire [31:0] _wdatatmp_T_14 = $signed(_T_21) >>> trueA[5:0]; // @[ALU.scala 113:58]
  wire [31:0] _wdatatmp_T_16 = trueB >> trueA[5:0]; // @[ALU.scala 116:27]
  wire  _T_34 = io_exeInfo_op == 8'h18; // @[ALU.scala 121:28]
  wire  _T_36 = trueA[1:0] != 2'h0; // @[ALU.scala 121:52]
  wire  _T_38 = io_exeInfo_op == 8'h1a; // @[ALU.scala 123:34]
  wire [31:0] _GEN_10 = io_exeInfo_op == 8'h14 | io_exeInfo_op == 8'h15 ? trueA : 32'h0; // @[ALU.scala 117:70 ALU.scala 119:18 ALU.scala 128:18]
  wire [31:0] _GEN_12 = io_exeInfo_op == 8'hc ? _wdatatmp_T_16 : _GEN_10; // @[ALU.scala 114:41 ALU.scala 116:18]
  wire [31:0] _GEN_14 = io_exeInfo_op == 8'hb ? _wdatatmp_T_14 : _GEN_12; // @[ALU.scala 111:41 ALU.scala 113:18]
  wire [94:0] _GEN_16 = io_exeInfo_op == 8'ha ? _wdatatmp_T_10 : {{63'd0}, _GEN_14}; // @[ALU.scala 108:41 ALU.scala 110:18]
  wire [94:0] _GEN_18 = io_exeInfo_op == 8'h9 ? {{63'd0}, _wdatatmp_T_8} : _GEN_16; // @[ALU.scala 105:41 ALU.scala 107:18]
  wire [94:0] _GEN_20 = io_exeInfo_op == 8'h8 ? {{63'd0}, _wdatatmp_T_7} : _GEN_18; // @[ALU.scala 102:40 ALU.scala 104:18]
  wire [94:0] _GEN_22 = io_exeInfo_op == 8'h7 ? {{63'd0}, _wdatatmp_T_6} : _GEN_20; // @[ALU.scala 99:41 ALU.scala 101:18]
  wire [94:0] _GEN_24 = io_exeInfo_op == 8'h6 ? {{63'd0}, _wdatatmp_T_5} : _GEN_22; // @[ALU.scala 96:41 ALU.scala 98:18]
  wire [94:0] _GEN_26 = io_exeInfo_op == 8'h5 ? {{63'd0}, io_mulans} : _GEN_24; // @[ALU.scala 92:41 ALU.scala 95:18]
  wire [94:0] _GEN_28 = io_exeInfo_op == 8'h4 ? {{94'd0}, _T_22} : _GEN_26; // @[ALU.scala 85:41]
  wire [94:0] _GEN_30 = io_exeInfo_op == 8'h3 ? {{63'd0}, _GEN_5} : _GEN_28; // @[ALU.scala 77:41]
  wire [94:0] _GEN_32 = io_exeInfo_op == 8'h2 ? {{63'd0}, addAns[31:0]} : _GEN_30; // @[ALU.scala 74:42 ALU.scala 76:18]
  wire [94:0] _GEN_34 = io_exeInfo_op == 8'h1 ? {{63'd0}, _GEN_3} : _GEN_32; // @[ALU.scala 66:35]
  wire  _T_47 = io_exeInfo_op == 8'h17; // @[ALU.scala 142:24]
  wire [2:0] _GEN_36 = _T_36 ? 3'h4 : 3'h1; // @[ALU.scala 153:33 ALU.scala 154:32 ALU.scala 156:32]
  wire [7:0] io_wdata_hi_lo = io_exeInfo_OperB[7:0]; // @[ALU.scala 166:55]
  wire [31:0] _io_wdata_T = {16'h0,io_wdata_hi_lo,8'h0}; // @[Cat.scala 30:58]
  wire [31:0] _io_wdata_T_1 = {8'h0,io_wdata_hi_lo,16'h0}; // @[Cat.scala 30:58]
  wire [31:0] _io_wdata_T_2 = {io_wdata_hi_lo,24'h0}; // @[Cat.scala 30:58]
  wire [31:0] _GEN_37 = io_memInfo_memAddr[1:0] == 2'h2 ? _io_wdata_T_1 : _io_wdata_T_2; // @[ALU.scala 167:52 ALU.scala 168:22 ALU.scala 170:22]
  wire [31:0] _GEN_38 = io_memInfo_memAddr[1:0] == 2'h1 ? _io_wdata_T : _GEN_37; // @[ALU.scala 165:52 ALU.scala 166:22]
  wire [31:0] _GEN_39 = io_memInfo_memAddr[1:0] == 2'h0 ? io_exeInfo_OperB : _GEN_38; // @[ALU.scala 163:46 ALU.scala 164:22]
  wire [2:0] _GEN_40 = _T_36 ? 3'h4 : 3'h3; // @[ALU.scala 177:33 ALU.scala 178:32 ALU.scala 180:32]
  wire [31:0] _GEN_41 = _T_38 ? io_exeInfo_OperB : 32'h0; // @[ALU.scala 172:40 ALU.scala 173:18 ALU.scala 186:18]
  wire [31:0] _GEN_43 = _T_38 ? io_exeInfo_OperA : 32'h80400000; // @[ALU.scala 172:40 ALU.scala 175:17 ALU.scala 185:17]
  wire [2:0] _GEN_45 = _T_38 ? _GEN_40 : 3'h4; // @[ALU.scala 172:40 ALU.scala 188:28]
  wire  _GEN_46 = io_exeInfo_op == 8'h19 | _T_38; // @[ALU.scala 158:40 ALU.scala 159:15]
  wire [31:0] _GEN_47 = io_exeInfo_op == 8'h19 ? io_exeInfo_OperA : _GEN_43; // @[ALU.scala 158:40 ALU.scala 160:17]
  wire [1:0] _GEN_48 = io_exeInfo_op == 8'h19 ? 2'h0 : 2'h2; // @[ALU.scala 158:40 ALU.scala 161:17]
  wire [2:0] _GEN_49 = io_exeInfo_op == 8'h19 ? 3'h2 : _GEN_45; // @[ALU.scala 158:40 ALU.scala 162:28]
  wire [31:0] _GEN_50 = io_exeInfo_op == 8'h19 ? _GEN_39 : _GEN_41; // @[ALU.scala 158:40]
  wire  _GEN_51 = _T_34 ? 1'h0 : _GEN_46; // @[ALU.scala 148:40 ALU.scala 149:15]
  wire [31:0] _GEN_52 = _T_34 ? io_exeInfo_OperA : _GEN_47; // @[ALU.scala 148:40 ALU.scala 150:17]
  wire [1:0] _GEN_53 = _T_34 ? 2'h2 : _GEN_48; // @[ALU.scala 148:40 ALU.scala 151:17]
  wire [31:0] _GEN_54 = _T_34 ? 32'h0 : _GEN_50; // @[ALU.scala 148:40 ALU.scala 152:18]
  wire [2:0] _GEN_55 = _T_34 ? _GEN_36 : _GEN_49; // @[ALU.scala 148:40]
  wire  _T_68 = ~io_exeInfo_OperA[22]; // @[ALU.scala 198:35]
  reg  state; // @[ALU.scala 207:24]
  wire  _T_69 = ~state; // @[ALU.scala 208:15]
  wire  _GEN_65 = ~state & _T_23; // @[ALU.scala 208:26 ALU.scala 215:15]
  assign io_ready_out = _T_23 & _T_69 ? 1'h0 : 1'h1; // @[ALU.scala 217:56 ALU.scala 218:22 ALU.scala 221:22]
  assign io_valid_out = _T_23 & _T_69 ? 1'h0 : 1'h1; // @[ALU.scala 217:56 ALU.scala 218:22 ALU.scala 221:22]
  assign io_memInfo_memType = io_exeInfo_op == 8'h17 ? 3'h0 : _GEN_55; // @[ALU.scala 142:34 ALU.scala 143:28]
  assign io_memInfo_memAddr = io_bypassFromMem2_regAddr != 5'h0 & io_exeInfo_AFromReg & io_exeInfo_ARegAddr ==
    io_bypassFromMem2_regAddr ? io_bypassFromMem2_regData : io_exeInfo_OperA; // @[ALU.scala 44:131 ALU.scala 45:15 ALU.scala 47:15]
  assign io_wbInfo_regwe = io_exeInfo_regwe; // @[ALU.scala 64:21]
  assign io_wbInfo_regAddr = io_exeInfo_wAddr; // @[ALU.scala 63:23]
  assign io_wbInfo_wData = _GEN_34[31:0]; // @[ALU.scala 35:24]
  assign io_bypassFromExe_regAddr = io_exeInfo_regwe & io_exeInfo_op != 8'h17 & io_exeInfo_op != 8'h18 ?
    io_exeInfo_wAddr : 5'h0; // @[ALU.scala 133:92 ALU.scala 134:34 ALU.scala 136:34]
  assign io_bypassFromExe_regData = _GEN_34[31:0]; // @[ALU.scala 35:24]
  assign io_isLBandLW = _T_47 | _T_34; // @[ALU.scala 192:34]
  assign io_wregAddr = io_exeInfo_wAddr; // @[ALU.scala 191:17]
  assign io_stallFromEXE = _GEN_46 & _T_68; // @[ALU.scala 197:61 ALU.scala 204:25]
  assign io_addr = io_exeInfo_op == 8'h17 ? io_exeInfo_OperA : _GEN_52; // @[ALU.scala 142:34 ALU.scala 145:17]
  assign io_wr = io_exeInfo_op == 8'h17 ? 1'h0 : _GEN_51; // @[ALU.scala 142:34 ALU.scala 144:15]
  assign io_size = io_exeInfo_op == 8'h17 ? 2'h0 : _GEN_53; // @[ALU.scala 142:34 ALU.scala 146:17]
  assign io_wdata = io_exeInfo_op == 8'h17 ? 32'h0 : _GEN_54; // @[ALU.scala 142:34 ALU.scala 147:18]
  assign io_OpA = io_bypassFromMem2_regAddr != 5'h0 & io_exeInfo_AFromReg & io_exeInfo_ARegAddr ==
    io_bypassFromMem2_regAddr ? io_bypassFromMem2_regData : io_exeInfo_OperA; // @[ALU.scala 44:131 ALU.scala 45:15 ALU.scala 47:15]
  assign io_OpB = _T & io_exeInfo_BFromReg & io_exeInfo_BRegAddr == io_bypassFromMem2_regAddr ?
    io_bypassFromMem2_regData : io_exeInfo_OperB; // @[ALU.scala 49:131 ALU.scala 50:15 ALU.scala 52:15]
  always @(posedge clock) begin
    if (reset) begin // @[ALU.scala 207:24]
      state <= 1'h0; // @[ALU.scala 207:24]
    end else begin
      state <= _GEN_65;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  state = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module BoothChooser(
  input  [31:0] io_X,
  input  [2:0]  io_y,
  output [31:0] io_P,
  output        io_c
);
  wire [32:0] _io_P_T = {io_X, 1'h0}; // @[BoothChooser.scala 23:23]
  wire [31:0] _io_P_T_4 = ~_io_P_T[31:0]; // @[BoothChooser.scala 26:17]
  wire [31:0] _io_P_T_5 = ~io_X; // @[BoothChooser.scala 29:17]
  wire  _T_6 = io_y == 3'h6; // @[BoothChooser.scala 31:21]
  wire [31:0] _GEN_0 = io_y == 3'h6 ? _io_P_T_5 : 32'h0; // @[BoothChooser.scala 31:29 BoothChooser.scala 32:14 BoothChooser.scala 35:14]
  wire [31:0] _GEN_2 = io_y == 3'h5 ? _io_P_T_5 : _GEN_0; // @[BoothChooser.scala 28:29 BoothChooser.scala 29:14]
  wire  _GEN_3 = io_y == 3'h5 | _T_6; // @[BoothChooser.scala 28:29 BoothChooser.scala 30:14]
  wire [31:0] _GEN_4 = io_y == 3'h4 ? _io_P_T_4 : _GEN_2; // @[BoothChooser.scala 25:29 BoothChooser.scala 26:14]
  wire  _GEN_5 = io_y == 3'h4 | _GEN_3; // @[BoothChooser.scala 25:29 BoothChooser.scala 27:14]
  wire [31:0] _GEN_6 = io_y == 3'h3 ? _io_P_T[31:0] : _GEN_4; // @[BoothChooser.scala 22:29 BoothChooser.scala 23:14]
  wire  _GEN_7 = io_y == 3'h3 ? 1'h0 : _GEN_5; // @[BoothChooser.scala 22:29 BoothChooser.scala 24:14]
  wire [31:0] _GEN_8 = io_y == 3'h2 ? io_X : _GEN_6; // @[BoothChooser.scala 19:29 BoothChooser.scala 20:14]
  wire  _GEN_9 = io_y == 3'h2 ? 1'h0 : _GEN_7; // @[BoothChooser.scala 19:29 BoothChooser.scala 21:14]
  wire [31:0] _GEN_10 = io_y == 3'h1 ? io_X : _GEN_8; // @[BoothChooser.scala 16:29 BoothChooser.scala 17:14]
  wire  _GEN_11 = io_y == 3'h1 ? 1'h0 : _GEN_9; // @[BoothChooser.scala 16:29 BoothChooser.scala 18:14]
  assign io_P = io_y == 3'h0 ? 32'h0 : _GEN_10; // @[BoothChooser.scala 13:23 BoothChooser.scala 14:14]
  assign io_c = io_y == 3'h0 ? 1'h0 : _GEN_11; // @[BoothChooser.scala 13:23 BoothChooser.scala 15:14]
endmodule
module Adder(
  input   io_A,
  input   io_B,
  input   io_Cin,
  output  io_Cout,
  output  io_S
);
  wire  _io_S_T = io_A ^ io_B; // @[Adder.scala 14:18]
  assign io_Cout = _io_S_T & io_Cin | io_A & io_B; // @[Adder.scala 15:41]
  assign io_S = io_A ^ io_B ^ io_Cin; // @[Adder.scala 14:25]
endmodule
module WallaceTree16(
  input  [15:0] io_N,
  output        io_S,
  output        io_C,
  input         io_Cin_0,
  input         io_Cin_1,
  input         io_Cin_2,
  input         io_Cin_3,
  input         io_Cin_4,
  input         io_Cin_5,
  input         io_Cin_6,
  input         io_Cin_7,
  input         io_Cin_8,
  input         io_Cin_9,
  input         io_Cin_10,
  input         io_Cin_11,
  input         io_Cin_12,
  input         io_Cin_13,
  input         io_Cin_14,
  output        io_Cout_0,
  output        io_Cout_1,
  output        io_Cout_2,
  output        io_Cout_3,
  output        io_Cout_4,
  output        io_Cout_5,
  output        io_Cout_6,
  output        io_Cout_7,
  output        io_Cout_8,
  output        io_Cout_9,
  output        io_Cout_10,
  output        io_Cout_11,
  output        io_Cout_12,
  output        io_Cout_13,
  output        io_Cout_14
);
  wire  adder0_io_A; // @[WallaceTree.scala 16:24]
  wire  adder0_io_B; // @[WallaceTree.scala 16:24]
  wire  adder0_io_Cin; // @[WallaceTree.scala 16:24]
  wire  adder0_io_Cout; // @[WallaceTree.scala 16:24]
  wire  adder0_io_S; // @[WallaceTree.scala 16:24]
  wire  adder1_io_A; // @[WallaceTree.scala 17:24]
  wire  adder1_io_B; // @[WallaceTree.scala 17:24]
  wire  adder1_io_Cin; // @[WallaceTree.scala 17:24]
  wire  adder1_io_Cout; // @[WallaceTree.scala 17:24]
  wire  adder1_io_S; // @[WallaceTree.scala 17:24]
  wire  adder2_io_A; // @[WallaceTree.scala 18:24]
  wire  adder2_io_B; // @[WallaceTree.scala 18:24]
  wire  adder2_io_Cin; // @[WallaceTree.scala 18:24]
  wire  adder2_io_Cout; // @[WallaceTree.scala 18:24]
  wire  adder2_io_S; // @[WallaceTree.scala 18:24]
  wire  adder3_io_A; // @[WallaceTree.scala 19:24]
  wire  adder3_io_B; // @[WallaceTree.scala 19:24]
  wire  adder3_io_Cin; // @[WallaceTree.scala 19:24]
  wire  adder3_io_Cout; // @[WallaceTree.scala 19:24]
  wire  adder3_io_S; // @[WallaceTree.scala 19:24]
  wire  adder4_io_A; // @[WallaceTree.scala 20:24]
  wire  adder4_io_B; // @[WallaceTree.scala 20:24]
  wire  adder4_io_Cin; // @[WallaceTree.scala 20:24]
  wire  adder4_io_Cout; // @[WallaceTree.scala 20:24]
  wire  adder4_io_S; // @[WallaceTree.scala 20:24]
  wire  adder5_io_A; // @[WallaceTree.scala 43:24]
  wire  adder5_io_B; // @[WallaceTree.scala 43:24]
  wire  adder5_io_Cin; // @[WallaceTree.scala 43:24]
  wire  adder5_io_Cout; // @[WallaceTree.scala 43:24]
  wire  adder5_io_S; // @[WallaceTree.scala 43:24]
  wire  adder6_io_A; // @[WallaceTree.scala 44:24]
  wire  adder6_io_B; // @[WallaceTree.scala 44:24]
  wire  adder6_io_Cin; // @[WallaceTree.scala 44:24]
  wire  adder6_io_Cout; // @[WallaceTree.scala 44:24]
  wire  adder6_io_S; // @[WallaceTree.scala 44:24]
  wire  adder7_io_A; // @[WallaceTree.scala 45:24]
  wire  adder7_io_B; // @[WallaceTree.scala 45:24]
  wire  adder7_io_Cin; // @[WallaceTree.scala 45:24]
  wire  adder7_io_Cout; // @[WallaceTree.scala 45:24]
  wire  adder7_io_S; // @[WallaceTree.scala 45:24]
  wire  adder8_io_A; // @[WallaceTree.scala 46:24]
  wire  adder8_io_B; // @[WallaceTree.scala 46:24]
  wire  adder8_io_Cin; // @[WallaceTree.scala 46:24]
  wire  adder8_io_Cout; // @[WallaceTree.scala 46:24]
  wire  adder8_io_S; // @[WallaceTree.scala 46:24]
  wire  adder9_io_A; // @[WallaceTree.scala 65:24]
  wire  adder9_io_B; // @[WallaceTree.scala 65:24]
  wire  adder9_io_Cin; // @[WallaceTree.scala 65:24]
  wire  adder9_io_Cout; // @[WallaceTree.scala 65:24]
  wire  adder9_io_S; // @[WallaceTree.scala 65:24]
  wire  adder10_io_A; // @[WallaceTree.scala 66:25]
  wire  adder10_io_B; // @[WallaceTree.scala 66:25]
  wire  adder10_io_Cin; // @[WallaceTree.scala 66:25]
  wire  adder10_io_Cout; // @[WallaceTree.scala 66:25]
  wire  adder10_io_S; // @[WallaceTree.scala 66:25]
  wire  adder11_io_A; // @[WallaceTree.scala 67:25]
  wire  adder11_io_B; // @[WallaceTree.scala 67:25]
  wire  adder11_io_Cin; // @[WallaceTree.scala 67:25]
  wire  adder11_io_Cout; // @[WallaceTree.scala 67:25]
  wire  adder11_io_S; // @[WallaceTree.scala 67:25]
  wire  adder12_io_A; // @[WallaceTree.scala 82:25]
  wire  adder12_io_B; // @[WallaceTree.scala 82:25]
  wire  adder12_io_Cin; // @[WallaceTree.scala 82:25]
  wire  adder12_io_Cout; // @[WallaceTree.scala 82:25]
  wire  adder12_io_S; // @[WallaceTree.scala 82:25]
  wire  adder13_io_A; // @[WallaceTree.scala 83:25]
  wire  adder13_io_B; // @[WallaceTree.scala 83:25]
  wire  adder13_io_Cin; // @[WallaceTree.scala 83:25]
  wire  adder13_io_Cout; // @[WallaceTree.scala 83:25]
  wire  adder13_io_S; // @[WallaceTree.scala 83:25]
  wire  adder14_io_A; // @[WallaceTree.scala 94:25]
  wire  adder14_io_B; // @[WallaceTree.scala 94:25]
  wire  adder14_io_Cin; // @[WallaceTree.scala 94:25]
  wire  adder14_io_Cout; // @[WallaceTree.scala 94:25]
  wire  adder14_io_S; // @[WallaceTree.scala 94:25]
  wire  adder15_io_A; // @[WallaceTree.scala 101:25]
  wire  adder15_io_B; // @[WallaceTree.scala 101:25]
  wire  adder15_io_Cin; // @[WallaceTree.scala 101:25]
  wire  adder15_io_Cout; // @[WallaceTree.scala 101:25]
  wire  adder15_io_S; // @[WallaceTree.scala 101:25]
  Adder adder0 ( // @[WallaceTree.scala 16:24]
    .io_A(adder0_io_A),
    .io_B(adder0_io_B),
    .io_Cin(adder0_io_Cin),
    .io_Cout(adder0_io_Cout),
    .io_S(adder0_io_S)
  );
  Adder adder1 ( // @[WallaceTree.scala 17:24]
    .io_A(adder1_io_A),
    .io_B(adder1_io_B),
    .io_Cin(adder1_io_Cin),
    .io_Cout(adder1_io_Cout),
    .io_S(adder1_io_S)
  );
  Adder adder2 ( // @[WallaceTree.scala 18:24]
    .io_A(adder2_io_A),
    .io_B(adder2_io_B),
    .io_Cin(adder2_io_Cin),
    .io_Cout(adder2_io_Cout),
    .io_S(adder2_io_S)
  );
  Adder adder3 ( // @[WallaceTree.scala 19:24]
    .io_A(adder3_io_A),
    .io_B(adder3_io_B),
    .io_Cin(adder3_io_Cin),
    .io_Cout(adder3_io_Cout),
    .io_S(adder3_io_S)
  );
  Adder adder4 ( // @[WallaceTree.scala 20:24]
    .io_A(adder4_io_A),
    .io_B(adder4_io_B),
    .io_Cin(adder4_io_Cin),
    .io_Cout(adder4_io_Cout),
    .io_S(adder4_io_S)
  );
  Adder adder5 ( // @[WallaceTree.scala 43:24]
    .io_A(adder5_io_A),
    .io_B(adder5_io_B),
    .io_Cin(adder5_io_Cin),
    .io_Cout(adder5_io_Cout),
    .io_S(adder5_io_S)
  );
  Adder adder6 ( // @[WallaceTree.scala 44:24]
    .io_A(adder6_io_A),
    .io_B(adder6_io_B),
    .io_Cin(adder6_io_Cin),
    .io_Cout(adder6_io_Cout),
    .io_S(adder6_io_S)
  );
  Adder adder7 ( // @[WallaceTree.scala 45:24]
    .io_A(adder7_io_A),
    .io_B(adder7_io_B),
    .io_Cin(adder7_io_Cin),
    .io_Cout(adder7_io_Cout),
    .io_S(adder7_io_S)
  );
  Adder adder8 ( // @[WallaceTree.scala 46:24]
    .io_A(adder8_io_A),
    .io_B(adder8_io_B),
    .io_Cin(adder8_io_Cin),
    .io_Cout(adder8_io_Cout),
    .io_S(adder8_io_S)
  );
  Adder adder9 ( // @[WallaceTree.scala 65:24]
    .io_A(adder9_io_A),
    .io_B(adder9_io_B),
    .io_Cin(adder9_io_Cin),
    .io_Cout(adder9_io_Cout),
    .io_S(adder9_io_S)
  );
  Adder adder10 ( // @[WallaceTree.scala 66:25]
    .io_A(adder10_io_A),
    .io_B(adder10_io_B),
    .io_Cin(adder10_io_Cin),
    .io_Cout(adder10_io_Cout),
    .io_S(adder10_io_S)
  );
  Adder adder11 ( // @[WallaceTree.scala 67:25]
    .io_A(adder11_io_A),
    .io_B(adder11_io_B),
    .io_Cin(adder11_io_Cin),
    .io_Cout(adder11_io_Cout),
    .io_S(adder11_io_S)
  );
  Adder adder12 ( // @[WallaceTree.scala 82:25]
    .io_A(adder12_io_A),
    .io_B(adder12_io_B),
    .io_Cin(adder12_io_Cin),
    .io_Cout(adder12_io_Cout),
    .io_S(adder12_io_S)
  );
  Adder adder13 ( // @[WallaceTree.scala 83:25]
    .io_A(adder13_io_A),
    .io_B(adder13_io_B),
    .io_Cin(adder13_io_Cin),
    .io_Cout(adder13_io_Cout),
    .io_S(adder13_io_S)
  );
  Adder adder14 ( // @[WallaceTree.scala 94:25]
    .io_A(adder14_io_A),
    .io_B(adder14_io_B),
    .io_Cin(adder14_io_Cin),
    .io_Cout(adder14_io_Cout),
    .io_S(adder14_io_S)
  );
  Adder adder15 ( // @[WallaceTree.scala 101:25]
    .io_A(adder15_io_A),
    .io_B(adder15_io_B),
    .io_Cin(adder15_io_Cin),
    .io_Cout(adder15_io_Cout),
    .io_S(adder15_io_S)
  );
  assign io_S = adder15_io_S; // @[WallaceTree.scala 126:10]
  assign io_C = adder15_io_Cout; // @[WallaceTree.scala 125:10]
  assign io_Cout_0 = adder0_io_Cout; // @[WallaceTree.scala 109:16]
  assign io_Cout_1 = adder1_io_Cout; // @[WallaceTree.scala 110:16]
  assign io_Cout_2 = adder2_io_Cout; // @[WallaceTree.scala 111:16]
  assign io_Cout_3 = adder3_io_Cout; // @[WallaceTree.scala 112:16]
  assign io_Cout_4 = adder4_io_Cout; // @[WallaceTree.scala 113:16]
  assign io_Cout_5 = adder5_io_Cout; // @[WallaceTree.scala 114:16]
  assign io_Cout_6 = adder6_io_Cout; // @[WallaceTree.scala 115:16]
  assign io_Cout_7 = adder7_io_Cout; // @[WallaceTree.scala 116:16]
  assign io_Cout_8 = adder8_io_Cout; // @[WallaceTree.scala 117:16]
  assign io_Cout_9 = adder9_io_Cout; // @[WallaceTree.scala 118:16]
  assign io_Cout_10 = adder10_io_Cout; // @[WallaceTree.scala 119:17]
  assign io_Cout_11 = adder11_io_Cout; // @[WallaceTree.scala 120:17]
  assign io_Cout_12 = adder12_io_Cout; // @[WallaceTree.scala 121:17]
  assign io_Cout_13 = adder13_io_Cout; // @[WallaceTree.scala 122:17]
  assign io_Cout_14 = adder14_io_Cout; // @[WallaceTree.scala 123:17]
  assign adder0_io_A = io_N[0]; // @[WallaceTree.scala 22:24]
  assign adder0_io_B = io_N[1]; // @[WallaceTree.scala 23:24]
  assign adder0_io_Cin = io_N[2]; // @[WallaceTree.scala 24:26]
  assign adder1_io_A = io_N[3]; // @[WallaceTree.scala 26:24]
  assign adder1_io_B = io_N[4]; // @[WallaceTree.scala 27:24]
  assign adder1_io_Cin = io_N[5]; // @[WallaceTree.scala 28:26]
  assign adder2_io_A = io_N[6]; // @[WallaceTree.scala 30:24]
  assign adder2_io_B = io_N[7]; // @[WallaceTree.scala 31:24]
  assign adder2_io_Cin = io_N[8]; // @[WallaceTree.scala 32:26]
  assign adder3_io_A = io_N[9]; // @[WallaceTree.scala 34:24]
  assign adder3_io_B = io_N[10]; // @[WallaceTree.scala 35:24]
  assign adder3_io_Cin = io_N[11]; // @[WallaceTree.scala 36:26]
  assign adder4_io_A = io_N[12]; // @[WallaceTree.scala 38:24]
  assign adder4_io_B = io_N[13]; // @[WallaceTree.scala 39:24]
  assign adder4_io_Cin = io_N[14]; // @[WallaceTree.scala 40:26]
  assign adder5_io_A = io_N[15]; // @[WallaceTree.scala 48:24]
  assign adder5_io_B = adder0_io_S; // @[WallaceTree.scala 49:17]
  assign adder5_io_Cin = adder1_io_S; // @[WallaceTree.scala 50:19]
  assign adder6_io_A = adder2_io_S; // @[WallaceTree.scala 52:17]
  assign adder6_io_B = adder3_io_S; // @[WallaceTree.scala 53:17]
  assign adder6_io_Cin = adder4_io_S; // @[WallaceTree.scala 54:19]
  assign adder7_io_A = io_Cin_0; // @[WallaceTree.scala 56:17]
  assign adder7_io_B = io_Cin_1; // @[WallaceTree.scala 57:17]
  assign adder7_io_Cin = io_Cin_2; // @[WallaceTree.scala 58:19]
  assign adder8_io_A = io_Cin_3; // @[WallaceTree.scala 60:17]
  assign adder8_io_B = io_Cin_4; // @[WallaceTree.scala 61:17]
  assign adder8_io_Cin = 1'h0; // @[WallaceTree.scala 62:19]
  assign adder9_io_A = adder5_io_S; // @[WallaceTree.scala 69:17]
  assign adder9_io_B = adder6_io_S; // @[WallaceTree.scala 70:17]
  assign adder9_io_Cin = adder7_io_S; // @[WallaceTree.scala 71:19]
  assign adder10_io_A = adder8_io_S; // @[WallaceTree.scala 73:18]
  assign adder10_io_B = io_Cin_5; // @[WallaceTree.scala 74:18]
  assign adder10_io_Cin = io_Cin_6; // @[WallaceTree.scala 75:20]
  assign adder11_io_A = io_Cin_7; // @[WallaceTree.scala 77:18]
  assign adder11_io_B = io_Cin_8; // @[WallaceTree.scala 78:18]
  assign adder11_io_Cin = 1'h0; // @[WallaceTree.scala 79:20]
  assign adder12_io_A = adder9_io_S; // @[WallaceTree.scala 85:18]
  assign adder12_io_B = adder10_io_S; // @[WallaceTree.scala 86:18]
  assign adder12_io_Cin = adder11_io_S; // @[WallaceTree.scala 87:20]
  assign adder13_io_A = io_Cin_9; // @[WallaceTree.scala 89:18]
  assign adder13_io_B = io_Cin_10; // @[WallaceTree.scala 90:18]
  assign adder13_io_Cin = io_Cin_11; // @[WallaceTree.scala 91:20]
  assign adder14_io_A = adder12_io_S; // @[WallaceTree.scala 96:18]
  assign adder14_io_B = adder13_io_S; // @[WallaceTree.scala 97:18]
  assign adder14_io_Cin = io_Cin_12; // @[WallaceTree.scala 98:20]
  assign adder15_io_A = adder14_io_S; // @[WallaceTree.scala 103:18]
  assign adder15_io_B = io_Cin_13; // @[WallaceTree.scala 104:18]
  assign adder15_io_Cin = io_Cin_14; // @[WallaceTree.scala 105:20]
endmodule
module MulModule(
  input         clock,
  input         reset,
  input  [31:0] io_OpA,
  input  [31:0] io_OpB,
  output [31:0] io_ans
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
`endif // RANDOMIZE_REG_INIT
  wire [31:0] bc0_io_X; // @[MulModule.scala 17:21]
  wire [2:0] bc0_io_y; // @[MulModule.scala 17:21]
  wire [31:0] bc0_io_P; // @[MulModule.scala 17:21]
  wire  bc0_io_c; // @[MulModule.scala 17:21]
  wire [31:0] bc1_io_X; // @[MulModule.scala 18:21]
  wire [2:0] bc1_io_y; // @[MulModule.scala 18:21]
  wire [31:0] bc1_io_P; // @[MulModule.scala 18:21]
  wire  bc1_io_c; // @[MulModule.scala 18:21]
  wire [31:0] bc2_io_X; // @[MulModule.scala 19:21]
  wire [2:0] bc2_io_y; // @[MulModule.scala 19:21]
  wire [31:0] bc2_io_P; // @[MulModule.scala 19:21]
  wire  bc2_io_c; // @[MulModule.scala 19:21]
  wire [31:0] bc3_io_X; // @[MulModule.scala 20:21]
  wire [2:0] bc3_io_y; // @[MulModule.scala 20:21]
  wire [31:0] bc3_io_P; // @[MulModule.scala 20:21]
  wire  bc3_io_c; // @[MulModule.scala 20:21]
  wire [31:0] bc4_io_X; // @[MulModule.scala 21:21]
  wire [2:0] bc4_io_y; // @[MulModule.scala 21:21]
  wire [31:0] bc4_io_P; // @[MulModule.scala 21:21]
  wire  bc4_io_c; // @[MulModule.scala 21:21]
  wire [31:0] bc5_io_X; // @[MulModule.scala 22:21]
  wire [2:0] bc5_io_y; // @[MulModule.scala 22:21]
  wire [31:0] bc5_io_P; // @[MulModule.scala 22:21]
  wire  bc5_io_c; // @[MulModule.scala 22:21]
  wire [31:0] bc6_io_X; // @[MulModule.scala 23:21]
  wire [2:0] bc6_io_y; // @[MulModule.scala 23:21]
  wire [31:0] bc6_io_P; // @[MulModule.scala 23:21]
  wire  bc6_io_c; // @[MulModule.scala 23:21]
  wire [31:0] bc7_io_X; // @[MulModule.scala 24:21]
  wire [2:0] bc7_io_y; // @[MulModule.scala 24:21]
  wire [31:0] bc7_io_P; // @[MulModule.scala 24:21]
  wire  bc7_io_c; // @[MulModule.scala 24:21]
  wire [31:0] bc8_io_X; // @[MulModule.scala 25:21]
  wire [2:0] bc8_io_y; // @[MulModule.scala 25:21]
  wire [31:0] bc8_io_P; // @[MulModule.scala 25:21]
  wire  bc8_io_c; // @[MulModule.scala 25:21]
  wire [31:0] bc9_io_X; // @[MulModule.scala 26:21]
  wire [2:0] bc9_io_y; // @[MulModule.scala 26:21]
  wire [31:0] bc9_io_P; // @[MulModule.scala 26:21]
  wire  bc9_io_c; // @[MulModule.scala 26:21]
  wire [31:0] bc10_io_X; // @[MulModule.scala 27:22]
  wire [2:0] bc10_io_y; // @[MulModule.scala 27:22]
  wire [31:0] bc10_io_P; // @[MulModule.scala 27:22]
  wire  bc10_io_c; // @[MulModule.scala 27:22]
  wire [31:0] bc11_io_X; // @[MulModule.scala 28:22]
  wire [2:0] bc11_io_y; // @[MulModule.scala 28:22]
  wire [31:0] bc11_io_P; // @[MulModule.scala 28:22]
  wire  bc11_io_c; // @[MulModule.scala 28:22]
  wire [31:0] bc12_io_X; // @[MulModule.scala 29:22]
  wire [2:0] bc12_io_y; // @[MulModule.scala 29:22]
  wire [31:0] bc12_io_P; // @[MulModule.scala 29:22]
  wire  bc12_io_c; // @[MulModule.scala 29:22]
  wire [31:0] bc13_io_X; // @[MulModule.scala 30:22]
  wire [2:0] bc13_io_y; // @[MulModule.scala 30:22]
  wire [31:0] bc13_io_P; // @[MulModule.scala 30:22]
  wire  bc13_io_c; // @[MulModule.scala 30:22]
  wire [31:0] bc14_io_X; // @[MulModule.scala 31:22]
  wire [2:0] bc14_io_y; // @[MulModule.scala 31:22]
  wire [31:0] bc14_io_P; // @[MulModule.scala 31:22]
  wire  bc14_io_c; // @[MulModule.scala 31:22]
  wire [31:0] bc15_io_X; // @[MulModule.scala 32:22]
  wire [2:0] bc15_io_y; // @[MulModule.scala 32:22]
  wire [31:0] bc15_io_P; // @[MulModule.scala 32:22]
  wire  bc15_io_c; // @[MulModule.scala 32:22]
  wire [15:0] wt0_io_N; // @[MulModule.scala 110:21]
  wire  wt0_io_S; // @[MulModule.scala 110:21]
  wire  wt0_io_C; // @[MulModule.scala 110:21]
  wire  wt0_io_Cin_0; // @[MulModule.scala 110:21]
  wire  wt0_io_Cin_1; // @[MulModule.scala 110:21]
  wire  wt0_io_Cin_2; // @[MulModule.scala 110:21]
  wire  wt0_io_Cin_3; // @[MulModule.scala 110:21]
  wire  wt0_io_Cin_4; // @[MulModule.scala 110:21]
  wire  wt0_io_Cin_5; // @[MulModule.scala 110:21]
  wire  wt0_io_Cin_6; // @[MulModule.scala 110:21]
  wire  wt0_io_Cin_7; // @[MulModule.scala 110:21]
  wire  wt0_io_Cin_8; // @[MulModule.scala 110:21]
  wire  wt0_io_Cin_9; // @[MulModule.scala 110:21]
  wire  wt0_io_Cin_10; // @[MulModule.scala 110:21]
  wire  wt0_io_Cin_11; // @[MulModule.scala 110:21]
  wire  wt0_io_Cin_12; // @[MulModule.scala 110:21]
  wire  wt0_io_Cin_13; // @[MulModule.scala 110:21]
  wire  wt0_io_Cin_14; // @[MulModule.scala 110:21]
  wire  wt0_io_Cout_0; // @[MulModule.scala 110:21]
  wire  wt0_io_Cout_1; // @[MulModule.scala 110:21]
  wire  wt0_io_Cout_2; // @[MulModule.scala 110:21]
  wire  wt0_io_Cout_3; // @[MulModule.scala 110:21]
  wire  wt0_io_Cout_4; // @[MulModule.scala 110:21]
  wire  wt0_io_Cout_5; // @[MulModule.scala 110:21]
  wire  wt0_io_Cout_6; // @[MulModule.scala 110:21]
  wire  wt0_io_Cout_7; // @[MulModule.scala 110:21]
  wire  wt0_io_Cout_8; // @[MulModule.scala 110:21]
  wire  wt0_io_Cout_9; // @[MulModule.scala 110:21]
  wire  wt0_io_Cout_10; // @[MulModule.scala 110:21]
  wire  wt0_io_Cout_11; // @[MulModule.scala 110:21]
  wire  wt0_io_Cout_12; // @[MulModule.scala 110:21]
  wire  wt0_io_Cout_13; // @[MulModule.scala 110:21]
  wire  wt0_io_Cout_14; // @[MulModule.scala 110:21]
  wire [15:0] wt1_io_N; // @[MulModule.scala 111:21]
  wire  wt1_io_S; // @[MulModule.scala 111:21]
  wire  wt1_io_C; // @[MulModule.scala 111:21]
  wire  wt1_io_Cin_0; // @[MulModule.scala 111:21]
  wire  wt1_io_Cin_1; // @[MulModule.scala 111:21]
  wire  wt1_io_Cin_2; // @[MulModule.scala 111:21]
  wire  wt1_io_Cin_3; // @[MulModule.scala 111:21]
  wire  wt1_io_Cin_4; // @[MulModule.scala 111:21]
  wire  wt1_io_Cin_5; // @[MulModule.scala 111:21]
  wire  wt1_io_Cin_6; // @[MulModule.scala 111:21]
  wire  wt1_io_Cin_7; // @[MulModule.scala 111:21]
  wire  wt1_io_Cin_8; // @[MulModule.scala 111:21]
  wire  wt1_io_Cin_9; // @[MulModule.scala 111:21]
  wire  wt1_io_Cin_10; // @[MulModule.scala 111:21]
  wire  wt1_io_Cin_11; // @[MulModule.scala 111:21]
  wire  wt1_io_Cin_12; // @[MulModule.scala 111:21]
  wire  wt1_io_Cin_13; // @[MulModule.scala 111:21]
  wire  wt1_io_Cin_14; // @[MulModule.scala 111:21]
  wire  wt1_io_Cout_0; // @[MulModule.scala 111:21]
  wire  wt1_io_Cout_1; // @[MulModule.scala 111:21]
  wire  wt1_io_Cout_2; // @[MulModule.scala 111:21]
  wire  wt1_io_Cout_3; // @[MulModule.scala 111:21]
  wire  wt1_io_Cout_4; // @[MulModule.scala 111:21]
  wire  wt1_io_Cout_5; // @[MulModule.scala 111:21]
  wire  wt1_io_Cout_6; // @[MulModule.scala 111:21]
  wire  wt1_io_Cout_7; // @[MulModule.scala 111:21]
  wire  wt1_io_Cout_8; // @[MulModule.scala 111:21]
  wire  wt1_io_Cout_9; // @[MulModule.scala 111:21]
  wire  wt1_io_Cout_10; // @[MulModule.scala 111:21]
  wire  wt1_io_Cout_11; // @[MulModule.scala 111:21]
  wire  wt1_io_Cout_12; // @[MulModule.scala 111:21]
  wire  wt1_io_Cout_13; // @[MulModule.scala 111:21]
  wire  wt1_io_Cout_14; // @[MulModule.scala 111:21]
  wire [15:0] wt2_io_N; // @[MulModule.scala 112:21]
  wire  wt2_io_S; // @[MulModule.scala 112:21]
  wire  wt2_io_C; // @[MulModule.scala 112:21]
  wire  wt2_io_Cin_0; // @[MulModule.scala 112:21]
  wire  wt2_io_Cin_1; // @[MulModule.scala 112:21]
  wire  wt2_io_Cin_2; // @[MulModule.scala 112:21]
  wire  wt2_io_Cin_3; // @[MulModule.scala 112:21]
  wire  wt2_io_Cin_4; // @[MulModule.scala 112:21]
  wire  wt2_io_Cin_5; // @[MulModule.scala 112:21]
  wire  wt2_io_Cin_6; // @[MulModule.scala 112:21]
  wire  wt2_io_Cin_7; // @[MulModule.scala 112:21]
  wire  wt2_io_Cin_8; // @[MulModule.scala 112:21]
  wire  wt2_io_Cin_9; // @[MulModule.scala 112:21]
  wire  wt2_io_Cin_10; // @[MulModule.scala 112:21]
  wire  wt2_io_Cin_11; // @[MulModule.scala 112:21]
  wire  wt2_io_Cin_12; // @[MulModule.scala 112:21]
  wire  wt2_io_Cin_13; // @[MulModule.scala 112:21]
  wire  wt2_io_Cin_14; // @[MulModule.scala 112:21]
  wire  wt2_io_Cout_0; // @[MulModule.scala 112:21]
  wire  wt2_io_Cout_1; // @[MulModule.scala 112:21]
  wire  wt2_io_Cout_2; // @[MulModule.scala 112:21]
  wire  wt2_io_Cout_3; // @[MulModule.scala 112:21]
  wire  wt2_io_Cout_4; // @[MulModule.scala 112:21]
  wire  wt2_io_Cout_5; // @[MulModule.scala 112:21]
  wire  wt2_io_Cout_6; // @[MulModule.scala 112:21]
  wire  wt2_io_Cout_7; // @[MulModule.scala 112:21]
  wire  wt2_io_Cout_8; // @[MulModule.scala 112:21]
  wire  wt2_io_Cout_9; // @[MulModule.scala 112:21]
  wire  wt2_io_Cout_10; // @[MulModule.scala 112:21]
  wire  wt2_io_Cout_11; // @[MulModule.scala 112:21]
  wire  wt2_io_Cout_12; // @[MulModule.scala 112:21]
  wire  wt2_io_Cout_13; // @[MulModule.scala 112:21]
  wire  wt2_io_Cout_14; // @[MulModule.scala 112:21]
  wire [15:0] wt3_io_N; // @[MulModule.scala 113:21]
  wire  wt3_io_S; // @[MulModule.scala 113:21]
  wire  wt3_io_C; // @[MulModule.scala 113:21]
  wire  wt3_io_Cin_0; // @[MulModule.scala 113:21]
  wire  wt3_io_Cin_1; // @[MulModule.scala 113:21]
  wire  wt3_io_Cin_2; // @[MulModule.scala 113:21]
  wire  wt3_io_Cin_3; // @[MulModule.scala 113:21]
  wire  wt3_io_Cin_4; // @[MulModule.scala 113:21]
  wire  wt3_io_Cin_5; // @[MulModule.scala 113:21]
  wire  wt3_io_Cin_6; // @[MulModule.scala 113:21]
  wire  wt3_io_Cin_7; // @[MulModule.scala 113:21]
  wire  wt3_io_Cin_8; // @[MulModule.scala 113:21]
  wire  wt3_io_Cin_9; // @[MulModule.scala 113:21]
  wire  wt3_io_Cin_10; // @[MulModule.scala 113:21]
  wire  wt3_io_Cin_11; // @[MulModule.scala 113:21]
  wire  wt3_io_Cin_12; // @[MulModule.scala 113:21]
  wire  wt3_io_Cin_13; // @[MulModule.scala 113:21]
  wire  wt3_io_Cin_14; // @[MulModule.scala 113:21]
  wire  wt3_io_Cout_0; // @[MulModule.scala 113:21]
  wire  wt3_io_Cout_1; // @[MulModule.scala 113:21]
  wire  wt3_io_Cout_2; // @[MulModule.scala 113:21]
  wire  wt3_io_Cout_3; // @[MulModule.scala 113:21]
  wire  wt3_io_Cout_4; // @[MulModule.scala 113:21]
  wire  wt3_io_Cout_5; // @[MulModule.scala 113:21]
  wire  wt3_io_Cout_6; // @[MulModule.scala 113:21]
  wire  wt3_io_Cout_7; // @[MulModule.scala 113:21]
  wire  wt3_io_Cout_8; // @[MulModule.scala 113:21]
  wire  wt3_io_Cout_9; // @[MulModule.scala 113:21]
  wire  wt3_io_Cout_10; // @[MulModule.scala 113:21]
  wire  wt3_io_Cout_11; // @[MulModule.scala 113:21]
  wire  wt3_io_Cout_12; // @[MulModule.scala 113:21]
  wire  wt3_io_Cout_13; // @[MulModule.scala 113:21]
  wire  wt3_io_Cout_14; // @[MulModule.scala 113:21]
  wire [15:0] wt4_io_N; // @[MulModule.scala 114:21]
  wire  wt4_io_S; // @[MulModule.scala 114:21]
  wire  wt4_io_C; // @[MulModule.scala 114:21]
  wire  wt4_io_Cin_0; // @[MulModule.scala 114:21]
  wire  wt4_io_Cin_1; // @[MulModule.scala 114:21]
  wire  wt4_io_Cin_2; // @[MulModule.scala 114:21]
  wire  wt4_io_Cin_3; // @[MulModule.scala 114:21]
  wire  wt4_io_Cin_4; // @[MulModule.scala 114:21]
  wire  wt4_io_Cin_5; // @[MulModule.scala 114:21]
  wire  wt4_io_Cin_6; // @[MulModule.scala 114:21]
  wire  wt4_io_Cin_7; // @[MulModule.scala 114:21]
  wire  wt4_io_Cin_8; // @[MulModule.scala 114:21]
  wire  wt4_io_Cin_9; // @[MulModule.scala 114:21]
  wire  wt4_io_Cin_10; // @[MulModule.scala 114:21]
  wire  wt4_io_Cin_11; // @[MulModule.scala 114:21]
  wire  wt4_io_Cin_12; // @[MulModule.scala 114:21]
  wire  wt4_io_Cin_13; // @[MulModule.scala 114:21]
  wire  wt4_io_Cin_14; // @[MulModule.scala 114:21]
  wire  wt4_io_Cout_0; // @[MulModule.scala 114:21]
  wire  wt4_io_Cout_1; // @[MulModule.scala 114:21]
  wire  wt4_io_Cout_2; // @[MulModule.scala 114:21]
  wire  wt4_io_Cout_3; // @[MulModule.scala 114:21]
  wire  wt4_io_Cout_4; // @[MulModule.scala 114:21]
  wire  wt4_io_Cout_5; // @[MulModule.scala 114:21]
  wire  wt4_io_Cout_6; // @[MulModule.scala 114:21]
  wire  wt4_io_Cout_7; // @[MulModule.scala 114:21]
  wire  wt4_io_Cout_8; // @[MulModule.scala 114:21]
  wire  wt4_io_Cout_9; // @[MulModule.scala 114:21]
  wire  wt4_io_Cout_10; // @[MulModule.scala 114:21]
  wire  wt4_io_Cout_11; // @[MulModule.scala 114:21]
  wire  wt4_io_Cout_12; // @[MulModule.scala 114:21]
  wire  wt4_io_Cout_13; // @[MulModule.scala 114:21]
  wire  wt4_io_Cout_14; // @[MulModule.scala 114:21]
  wire [15:0] wt5_io_N; // @[MulModule.scala 115:21]
  wire  wt5_io_S; // @[MulModule.scala 115:21]
  wire  wt5_io_C; // @[MulModule.scala 115:21]
  wire  wt5_io_Cin_0; // @[MulModule.scala 115:21]
  wire  wt5_io_Cin_1; // @[MulModule.scala 115:21]
  wire  wt5_io_Cin_2; // @[MulModule.scala 115:21]
  wire  wt5_io_Cin_3; // @[MulModule.scala 115:21]
  wire  wt5_io_Cin_4; // @[MulModule.scala 115:21]
  wire  wt5_io_Cin_5; // @[MulModule.scala 115:21]
  wire  wt5_io_Cin_6; // @[MulModule.scala 115:21]
  wire  wt5_io_Cin_7; // @[MulModule.scala 115:21]
  wire  wt5_io_Cin_8; // @[MulModule.scala 115:21]
  wire  wt5_io_Cin_9; // @[MulModule.scala 115:21]
  wire  wt5_io_Cin_10; // @[MulModule.scala 115:21]
  wire  wt5_io_Cin_11; // @[MulModule.scala 115:21]
  wire  wt5_io_Cin_12; // @[MulModule.scala 115:21]
  wire  wt5_io_Cin_13; // @[MulModule.scala 115:21]
  wire  wt5_io_Cin_14; // @[MulModule.scala 115:21]
  wire  wt5_io_Cout_0; // @[MulModule.scala 115:21]
  wire  wt5_io_Cout_1; // @[MulModule.scala 115:21]
  wire  wt5_io_Cout_2; // @[MulModule.scala 115:21]
  wire  wt5_io_Cout_3; // @[MulModule.scala 115:21]
  wire  wt5_io_Cout_4; // @[MulModule.scala 115:21]
  wire  wt5_io_Cout_5; // @[MulModule.scala 115:21]
  wire  wt5_io_Cout_6; // @[MulModule.scala 115:21]
  wire  wt5_io_Cout_7; // @[MulModule.scala 115:21]
  wire  wt5_io_Cout_8; // @[MulModule.scala 115:21]
  wire  wt5_io_Cout_9; // @[MulModule.scala 115:21]
  wire  wt5_io_Cout_10; // @[MulModule.scala 115:21]
  wire  wt5_io_Cout_11; // @[MulModule.scala 115:21]
  wire  wt5_io_Cout_12; // @[MulModule.scala 115:21]
  wire  wt5_io_Cout_13; // @[MulModule.scala 115:21]
  wire  wt5_io_Cout_14; // @[MulModule.scala 115:21]
  wire [15:0] wt6_io_N; // @[MulModule.scala 116:21]
  wire  wt6_io_S; // @[MulModule.scala 116:21]
  wire  wt6_io_C; // @[MulModule.scala 116:21]
  wire  wt6_io_Cin_0; // @[MulModule.scala 116:21]
  wire  wt6_io_Cin_1; // @[MulModule.scala 116:21]
  wire  wt6_io_Cin_2; // @[MulModule.scala 116:21]
  wire  wt6_io_Cin_3; // @[MulModule.scala 116:21]
  wire  wt6_io_Cin_4; // @[MulModule.scala 116:21]
  wire  wt6_io_Cin_5; // @[MulModule.scala 116:21]
  wire  wt6_io_Cin_6; // @[MulModule.scala 116:21]
  wire  wt6_io_Cin_7; // @[MulModule.scala 116:21]
  wire  wt6_io_Cin_8; // @[MulModule.scala 116:21]
  wire  wt6_io_Cin_9; // @[MulModule.scala 116:21]
  wire  wt6_io_Cin_10; // @[MulModule.scala 116:21]
  wire  wt6_io_Cin_11; // @[MulModule.scala 116:21]
  wire  wt6_io_Cin_12; // @[MulModule.scala 116:21]
  wire  wt6_io_Cin_13; // @[MulModule.scala 116:21]
  wire  wt6_io_Cin_14; // @[MulModule.scala 116:21]
  wire  wt6_io_Cout_0; // @[MulModule.scala 116:21]
  wire  wt6_io_Cout_1; // @[MulModule.scala 116:21]
  wire  wt6_io_Cout_2; // @[MulModule.scala 116:21]
  wire  wt6_io_Cout_3; // @[MulModule.scala 116:21]
  wire  wt6_io_Cout_4; // @[MulModule.scala 116:21]
  wire  wt6_io_Cout_5; // @[MulModule.scala 116:21]
  wire  wt6_io_Cout_6; // @[MulModule.scala 116:21]
  wire  wt6_io_Cout_7; // @[MulModule.scala 116:21]
  wire  wt6_io_Cout_8; // @[MulModule.scala 116:21]
  wire  wt6_io_Cout_9; // @[MulModule.scala 116:21]
  wire  wt6_io_Cout_10; // @[MulModule.scala 116:21]
  wire  wt6_io_Cout_11; // @[MulModule.scala 116:21]
  wire  wt6_io_Cout_12; // @[MulModule.scala 116:21]
  wire  wt6_io_Cout_13; // @[MulModule.scala 116:21]
  wire  wt6_io_Cout_14; // @[MulModule.scala 116:21]
  wire [15:0] wt7_io_N; // @[MulModule.scala 117:21]
  wire  wt7_io_S; // @[MulModule.scala 117:21]
  wire  wt7_io_C; // @[MulModule.scala 117:21]
  wire  wt7_io_Cin_0; // @[MulModule.scala 117:21]
  wire  wt7_io_Cin_1; // @[MulModule.scala 117:21]
  wire  wt7_io_Cin_2; // @[MulModule.scala 117:21]
  wire  wt7_io_Cin_3; // @[MulModule.scala 117:21]
  wire  wt7_io_Cin_4; // @[MulModule.scala 117:21]
  wire  wt7_io_Cin_5; // @[MulModule.scala 117:21]
  wire  wt7_io_Cin_6; // @[MulModule.scala 117:21]
  wire  wt7_io_Cin_7; // @[MulModule.scala 117:21]
  wire  wt7_io_Cin_8; // @[MulModule.scala 117:21]
  wire  wt7_io_Cin_9; // @[MulModule.scala 117:21]
  wire  wt7_io_Cin_10; // @[MulModule.scala 117:21]
  wire  wt7_io_Cin_11; // @[MulModule.scala 117:21]
  wire  wt7_io_Cin_12; // @[MulModule.scala 117:21]
  wire  wt7_io_Cin_13; // @[MulModule.scala 117:21]
  wire  wt7_io_Cin_14; // @[MulModule.scala 117:21]
  wire  wt7_io_Cout_0; // @[MulModule.scala 117:21]
  wire  wt7_io_Cout_1; // @[MulModule.scala 117:21]
  wire  wt7_io_Cout_2; // @[MulModule.scala 117:21]
  wire  wt7_io_Cout_3; // @[MulModule.scala 117:21]
  wire  wt7_io_Cout_4; // @[MulModule.scala 117:21]
  wire  wt7_io_Cout_5; // @[MulModule.scala 117:21]
  wire  wt7_io_Cout_6; // @[MulModule.scala 117:21]
  wire  wt7_io_Cout_7; // @[MulModule.scala 117:21]
  wire  wt7_io_Cout_8; // @[MulModule.scala 117:21]
  wire  wt7_io_Cout_9; // @[MulModule.scala 117:21]
  wire  wt7_io_Cout_10; // @[MulModule.scala 117:21]
  wire  wt7_io_Cout_11; // @[MulModule.scala 117:21]
  wire  wt7_io_Cout_12; // @[MulModule.scala 117:21]
  wire  wt7_io_Cout_13; // @[MulModule.scala 117:21]
  wire  wt7_io_Cout_14; // @[MulModule.scala 117:21]
  wire [15:0] wt8_io_N; // @[MulModule.scala 118:21]
  wire  wt8_io_S; // @[MulModule.scala 118:21]
  wire  wt8_io_C; // @[MulModule.scala 118:21]
  wire  wt8_io_Cin_0; // @[MulModule.scala 118:21]
  wire  wt8_io_Cin_1; // @[MulModule.scala 118:21]
  wire  wt8_io_Cin_2; // @[MulModule.scala 118:21]
  wire  wt8_io_Cin_3; // @[MulModule.scala 118:21]
  wire  wt8_io_Cin_4; // @[MulModule.scala 118:21]
  wire  wt8_io_Cin_5; // @[MulModule.scala 118:21]
  wire  wt8_io_Cin_6; // @[MulModule.scala 118:21]
  wire  wt8_io_Cin_7; // @[MulModule.scala 118:21]
  wire  wt8_io_Cin_8; // @[MulModule.scala 118:21]
  wire  wt8_io_Cin_9; // @[MulModule.scala 118:21]
  wire  wt8_io_Cin_10; // @[MulModule.scala 118:21]
  wire  wt8_io_Cin_11; // @[MulModule.scala 118:21]
  wire  wt8_io_Cin_12; // @[MulModule.scala 118:21]
  wire  wt8_io_Cin_13; // @[MulModule.scala 118:21]
  wire  wt8_io_Cin_14; // @[MulModule.scala 118:21]
  wire  wt8_io_Cout_0; // @[MulModule.scala 118:21]
  wire  wt8_io_Cout_1; // @[MulModule.scala 118:21]
  wire  wt8_io_Cout_2; // @[MulModule.scala 118:21]
  wire  wt8_io_Cout_3; // @[MulModule.scala 118:21]
  wire  wt8_io_Cout_4; // @[MulModule.scala 118:21]
  wire  wt8_io_Cout_5; // @[MulModule.scala 118:21]
  wire  wt8_io_Cout_6; // @[MulModule.scala 118:21]
  wire  wt8_io_Cout_7; // @[MulModule.scala 118:21]
  wire  wt8_io_Cout_8; // @[MulModule.scala 118:21]
  wire  wt8_io_Cout_9; // @[MulModule.scala 118:21]
  wire  wt8_io_Cout_10; // @[MulModule.scala 118:21]
  wire  wt8_io_Cout_11; // @[MulModule.scala 118:21]
  wire  wt8_io_Cout_12; // @[MulModule.scala 118:21]
  wire  wt8_io_Cout_13; // @[MulModule.scala 118:21]
  wire  wt8_io_Cout_14; // @[MulModule.scala 118:21]
  wire [15:0] wt9_io_N; // @[MulModule.scala 119:21]
  wire  wt9_io_S; // @[MulModule.scala 119:21]
  wire  wt9_io_C; // @[MulModule.scala 119:21]
  wire  wt9_io_Cin_0; // @[MulModule.scala 119:21]
  wire  wt9_io_Cin_1; // @[MulModule.scala 119:21]
  wire  wt9_io_Cin_2; // @[MulModule.scala 119:21]
  wire  wt9_io_Cin_3; // @[MulModule.scala 119:21]
  wire  wt9_io_Cin_4; // @[MulModule.scala 119:21]
  wire  wt9_io_Cin_5; // @[MulModule.scala 119:21]
  wire  wt9_io_Cin_6; // @[MulModule.scala 119:21]
  wire  wt9_io_Cin_7; // @[MulModule.scala 119:21]
  wire  wt9_io_Cin_8; // @[MulModule.scala 119:21]
  wire  wt9_io_Cin_9; // @[MulModule.scala 119:21]
  wire  wt9_io_Cin_10; // @[MulModule.scala 119:21]
  wire  wt9_io_Cin_11; // @[MulModule.scala 119:21]
  wire  wt9_io_Cin_12; // @[MulModule.scala 119:21]
  wire  wt9_io_Cin_13; // @[MulModule.scala 119:21]
  wire  wt9_io_Cin_14; // @[MulModule.scala 119:21]
  wire  wt9_io_Cout_0; // @[MulModule.scala 119:21]
  wire  wt9_io_Cout_1; // @[MulModule.scala 119:21]
  wire  wt9_io_Cout_2; // @[MulModule.scala 119:21]
  wire  wt9_io_Cout_3; // @[MulModule.scala 119:21]
  wire  wt9_io_Cout_4; // @[MulModule.scala 119:21]
  wire  wt9_io_Cout_5; // @[MulModule.scala 119:21]
  wire  wt9_io_Cout_6; // @[MulModule.scala 119:21]
  wire  wt9_io_Cout_7; // @[MulModule.scala 119:21]
  wire  wt9_io_Cout_8; // @[MulModule.scala 119:21]
  wire  wt9_io_Cout_9; // @[MulModule.scala 119:21]
  wire  wt9_io_Cout_10; // @[MulModule.scala 119:21]
  wire  wt9_io_Cout_11; // @[MulModule.scala 119:21]
  wire  wt9_io_Cout_12; // @[MulModule.scala 119:21]
  wire  wt9_io_Cout_13; // @[MulModule.scala 119:21]
  wire  wt9_io_Cout_14; // @[MulModule.scala 119:21]
  wire [15:0] wt10_io_N; // @[MulModule.scala 120:22]
  wire  wt10_io_S; // @[MulModule.scala 120:22]
  wire  wt10_io_C; // @[MulModule.scala 120:22]
  wire  wt10_io_Cin_0; // @[MulModule.scala 120:22]
  wire  wt10_io_Cin_1; // @[MulModule.scala 120:22]
  wire  wt10_io_Cin_2; // @[MulModule.scala 120:22]
  wire  wt10_io_Cin_3; // @[MulModule.scala 120:22]
  wire  wt10_io_Cin_4; // @[MulModule.scala 120:22]
  wire  wt10_io_Cin_5; // @[MulModule.scala 120:22]
  wire  wt10_io_Cin_6; // @[MulModule.scala 120:22]
  wire  wt10_io_Cin_7; // @[MulModule.scala 120:22]
  wire  wt10_io_Cin_8; // @[MulModule.scala 120:22]
  wire  wt10_io_Cin_9; // @[MulModule.scala 120:22]
  wire  wt10_io_Cin_10; // @[MulModule.scala 120:22]
  wire  wt10_io_Cin_11; // @[MulModule.scala 120:22]
  wire  wt10_io_Cin_12; // @[MulModule.scala 120:22]
  wire  wt10_io_Cin_13; // @[MulModule.scala 120:22]
  wire  wt10_io_Cin_14; // @[MulModule.scala 120:22]
  wire  wt10_io_Cout_0; // @[MulModule.scala 120:22]
  wire  wt10_io_Cout_1; // @[MulModule.scala 120:22]
  wire  wt10_io_Cout_2; // @[MulModule.scala 120:22]
  wire  wt10_io_Cout_3; // @[MulModule.scala 120:22]
  wire  wt10_io_Cout_4; // @[MulModule.scala 120:22]
  wire  wt10_io_Cout_5; // @[MulModule.scala 120:22]
  wire  wt10_io_Cout_6; // @[MulModule.scala 120:22]
  wire  wt10_io_Cout_7; // @[MulModule.scala 120:22]
  wire  wt10_io_Cout_8; // @[MulModule.scala 120:22]
  wire  wt10_io_Cout_9; // @[MulModule.scala 120:22]
  wire  wt10_io_Cout_10; // @[MulModule.scala 120:22]
  wire  wt10_io_Cout_11; // @[MulModule.scala 120:22]
  wire  wt10_io_Cout_12; // @[MulModule.scala 120:22]
  wire  wt10_io_Cout_13; // @[MulModule.scala 120:22]
  wire  wt10_io_Cout_14; // @[MulModule.scala 120:22]
  wire [15:0] wt11_io_N; // @[MulModule.scala 121:22]
  wire  wt11_io_S; // @[MulModule.scala 121:22]
  wire  wt11_io_C; // @[MulModule.scala 121:22]
  wire  wt11_io_Cin_0; // @[MulModule.scala 121:22]
  wire  wt11_io_Cin_1; // @[MulModule.scala 121:22]
  wire  wt11_io_Cin_2; // @[MulModule.scala 121:22]
  wire  wt11_io_Cin_3; // @[MulModule.scala 121:22]
  wire  wt11_io_Cin_4; // @[MulModule.scala 121:22]
  wire  wt11_io_Cin_5; // @[MulModule.scala 121:22]
  wire  wt11_io_Cin_6; // @[MulModule.scala 121:22]
  wire  wt11_io_Cin_7; // @[MulModule.scala 121:22]
  wire  wt11_io_Cin_8; // @[MulModule.scala 121:22]
  wire  wt11_io_Cin_9; // @[MulModule.scala 121:22]
  wire  wt11_io_Cin_10; // @[MulModule.scala 121:22]
  wire  wt11_io_Cin_11; // @[MulModule.scala 121:22]
  wire  wt11_io_Cin_12; // @[MulModule.scala 121:22]
  wire  wt11_io_Cin_13; // @[MulModule.scala 121:22]
  wire  wt11_io_Cin_14; // @[MulModule.scala 121:22]
  wire  wt11_io_Cout_0; // @[MulModule.scala 121:22]
  wire  wt11_io_Cout_1; // @[MulModule.scala 121:22]
  wire  wt11_io_Cout_2; // @[MulModule.scala 121:22]
  wire  wt11_io_Cout_3; // @[MulModule.scala 121:22]
  wire  wt11_io_Cout_4; // @[MulModule.scala 121:22]
  wire  wt11_io_Cout_5; // @[MulModule.scala 121:22]
  wire  wt11_io_Cout_6; // @[MulModule.scala 121:22]
  wire  wt11_io_Cout_7; // @[MulModule.scala 121:22]
  wire  wt11_io_Cout_8; // @[MulModule.scala 121:22]
  wire  wt11_io_Cout_9; // @[MulModule.scala 121:22]
  wire  wt11_io_Cout_10; // @[MulModule.scala 121:22]
  wire  wt11_io_Cout_11; // @[MulModule.scala 121:22]
  wire  wt11_io_Cout_12; // @[MulModule.scala 121:22]
  wire  wt11_io_Cout_13; // @[MulModule.scala 121:22]
  wire  wt11_io_Cout_14; // @[MulModule.scala 121:22]
  wire [15:0] wt12_io_N; // @[MulModule.scala 122:22]
  wire  wt12_io_S; // @[MulModule.scala 122:22]
  wire  wt12_io_C; // @[MulModule.scala 122:22]
  wire  wt12_io_Cin_0; // @[MulModule.scala 122:22]
  wire  wt12_io_Cin_1; // @[MulModule.scala 122:22]
  wire  wt12_io_Cin_2; // @[MulModule.scala 122:22]
  wire  wt12_io_Cin_3; // @[MulModule.scala 122:22]
  wire  wt12_io_Cin_4; // @[MulModule.scala 122:22]
  wire  wt12_io_Cin_5; // @[MulModule.scala 122:22]
  wire  wt12_io_Cin_6; // @[MulModule.scala 122:22]
  wire  wt12_io_Cin_7; // @[MulModule.scala 122:22]
  wire  wt12_io_Cin_8; // @[MulModule.scala 122:22]
  wire  wt12_io_Cin_9; // @[MulModule.scala 122:22]
  wire  wt12_io_Cin_10; // @[MulModule.scala 122:22]
  wire  wt12_io_Cin_11; // @[MulModule.scala 122:22]
  wire  wt12_io_Cin_12; // @[MulModule.scala 122:22]
  wire  wt12_io_Cin_13; // @[MulModule.scala 122:22]
  wire  wt12_io_Cin_14; // @[MulModule.scala 122:22]
  wire  wt12_io_Cout_0; // @[MulModule.scala 122:22]
  wire  wt12_io_Cout_1; // @[MulModule.scala 122:22]
  wire  wt12_io_Cout_2; // @[MulModule.scala 122:22]
  wire  wt12_io_Cout_3; // @[MulModule.scala 122:22]
  wire  wt12_io_Cout_4; // @[MulModule.scala 122:22]
  wire  wt12_io_Cout_5; // @[MulModule.scala 122:22]
  wire  wt12_io_Cout_6; // @[MulModule.scala 122:22]
  wire  wt12_io_Cout_7; // @[MulModule.scala 122:22]
  wire  wt12_io_Cout_8; // @[MulModule.scala 122:22]
  wire  wt12_io_Cout_9; // @[MulModule.scala 122:22]
  wire  wt12_io_Cout_10; // @[MulModule.scala 122:22]
  wire  wt12_io_Cout_11; // @[MulModule.scala 122:22]
  wire  wt12_io_Cout_12; // @[MulModule.scala 122:22]
  wire  wt12_io_Cout_13; // @[MulModule.scala 122:22]
  wire  wt12_io_Cout_14; // @[MulModule.scala 122:22]
  wire [15:0] wt13_io_N; // @[MulModule.scala 123:22]
  wire  wt13_io_S; // @[MulModule.scala 123:22]
  wire  wt13_io_C; // @[MulModule.scala 123:22]
  wire  wt13_io_Cin_0; // @[MulModule.scala 123:22]
  wire  wt13_io_Cin_1; // @[MulModule.scala 123:22]
  wire  wt13_io_Cin_2; // @[MulModule.scala 123:22]
  wire  wt13_io_Cin_3; // @[MulModule.scala 123:22]
  wire  wt13_io_Cin_4; // @[MulModule.scala 123:22]
  wire  wt13_io_Cin_5; // @[MulModule.scala 123:22]
  wire  wt13_io_Cin_6; // @[MulModule.scala 123:22]
  wire  wt13_io_Cin_7; // @[MulModule.scala 123:22]
  wire  wt13_io_Cin_8; // @[MulModule.scala 123:22]
  wire  wt13_io_Cin_9; // @[MulModule.scala 123:22]
  wire  wt13_io_Cin_10; // @[MulModule.scala 123:22]
  wire  wt13_io_Cin_11; // @[MulModule.scala 123:22]
  wire  wt13_io_Cin_12; // @[MulModule.scala 123:22]
  wire  wt13_io_Cin_13; // @[MulModule.scala 123:22]
  wire  wt13_io_Cin_14; // @[MulModule.scala 123:22]
  wire  wt13_io_Cout_0; // @[MulModule.scala 123:22]
  wire  wt13_io_Cout_1; // @[MulModule.scala 123:22]
  wire  wt13_io_Cout_2; // @[MulModule.scala 123:22]
  wire  wt13_io_Cout_3; // @[MulModule.scala 123:22]
  wire  wt13_io_Cout_4; // @[MulModule.scala 123:22]
  wire  wt13_io_Cout_5; // @[MulModule.scala 123:22]
  wire  wt13_io_Cout_6; // @[MulModule.scala 123:22]
  wire  wt13_io_Cout_7; // @[MulModule.scala 123:22]
  wire  wt13_io_Cout_8; // @[MulModule.scala 123:22]
  wire  wt13_io_Cout_9; // @[MulModule.scala 123:22]
  wire  wt13_io_Cout_10; // @[MulModule.scala 123:22]
  wire  wt13_io_Cout_11; // @[MulModule.scala 123:22]
  wire  wt13_io_Cout_12; // @[MulModule.scala 123:22]
  wire  wt13_io_Cout_13; // @[MulModule.scala 123:22]
  wire  wt13_io_Cout_14; // @[MulModule.scala 123:22]
  wire [15:0] wt14_io_N; // @[MulModule.scala 124:22]
  wire  wt14_io_S; // @[MulModule.scala 124:22]
  wire  wt14_io_C; // @[MulModule.scala 124:22]
  wire  wt14_io_Cin_0; // @[MulModule.scala 124:22]
  wire  wt14_io_Cin_1; // @[MulModule.scala 124:22]
  wire  wt14_io_Cin_2; // @[MulModule.scala 124:22]
  wire  wt14_io_Cin_3; // @[MulModule.scala 124:22]
  wire  wt14_io_Cin_4; // @[MulModule.scala 124:22]
  wire  wt14_io_Cin_5; // @[MulModule.scala 124:22]
  wire  wt14_io_Cin_6; // @[MulModule.scala 124:22]
  wire  wt14_io_Cin_7; // @[MulModule.scala 124:22]
  wire  wt14_io_Cin_8; // @[MulModule.scala 124:22]
  wire  wt14_io_Cin_9; // @[MulModule.scala 124:22]
  wire  wt14_io_Cin_10; // @[MulModule.scala 124:22]
  wire  wt14_io_Cin_11; // @[MulModule.scala 124:22]
  wire  wt14_io_Cin_12; // @[MulModule.scala 124:22]
  wire  wt14_io_Cin_13; // @[MulModule.scala 124:22]
  wire  wt14_io_Cin_14; // @[MulModule.scala 124:22]
  wire  wt14_io_Cout_0; // @[MulModule.scala 124:22]
  wire  wt14_io_Cout_1; // @[MulModule.scala 124:22]
  wire  wt14_io_Cout_2; // @[MulModule.scala 124:22]
  wire  wt14_io_Cout_3; // @[MulModule.scala 124:22]
  wire  wt14_io_Cout_4; // @[MulModule.scala 124:22]
  wire  wt14_io_Cout_5; // @[MulModule.scala 124:22]
  wire  wt14_io_Cout_6; // @[MulModule.scala 124:22]
  wire  wt14_io_Cout_7; // @[MulModule.scala 124:22]
  wire  wt14_io_Cout_8; // @[MulModule.scala 124:22]
  wire  wt14_io_Cout_9; // @[MulModule.scala 124:22]
  wire  wt14_io_Cout_10; // @[MulModule.scala 124:22]
  wire  wt14_io_Cout_11; // @[MulModule.scala 124:22]
  wire  wt14_io_Cout_12; // @[MulModule.scala 124:22]
  wire  wt14_io_Cout_13; // @[MulModule.scala 124:22]
  wire  wt14_io_Cout_14; // @[MulModule.scala 124:22]
  wire [15:0] wt15_io_N; // @[MulModule.scala 125:22]
  wire  wt15_io_S; // @[MulModule.scala 125:22]
  wire  wt15_io_C; // @[MulModule.scala 125:22]
  wire  wt15_io_Cin_0; // @[MulModule.scala 125:22]
  wire  wt15_io_Cin_1; // @[MulModule.scala 125:22]
  wire  wt15_io_Cin_2; // @[MulModule.scala 125:22]
  wire  wt15_io_Cin_3; // @[MulModule.scala 125:22]
  wire  wt15_io_Cin_4; // @[MulModule.scala 125:22]
  wire  wt15_io_Cin_5; // @[MulModule.scala 125:22]
  wire  wt15_io_Cin_6; // @[MulModule.scala 125:22]
  wire  wt15_io_Cin_7; // @[MulModule.scala 125:22]
  wire  wt15_io_Cin_8; // @[MulModule.scala 125:22]
  wire  wt15_io_Cin_9; // @[MulModule.scala 125:22]
  wire  wt15_io_Cin_10; // @[MulModule.scala 125:22]
  wire  wt15_io_Cin_11; // @[MulModule.scala 125:22]
  wire  wt15_io_Cin_12; // @[MulModule.scala 125:22]
  wire  wt15_io_Cin_13; // @[MulModule.scala 125:22]
  wire  wt15_io_Cin_14; // @[MulModule.scala 125:22]
  wire  wt15_io_Cout_0; // @[MulModule.scala 125:22]
  wire  wt15_io_Cout_1; // @[MulModule.scala 125:22]
  wire  wt15_io_Cout_2; // @[MulModule.scala 125:22]
  wire  wt15_io_Cout_3; // @[MulModule.scala 125:22]
  wire  wt15_io_Cout_4; // @[MulModule.scala 125:22]
  wire  wt15_io_Cout_5; // @[MulModule.scala 125:22]
  wire  wt15_io_Cout_6; // @[MulModule.scala 125:22]
  wire  wt15_io_Cout_7; // @[MulModule.scala 125:22]
  wire  wt15_io_Cout_8; // @[MulModule.scala 125:22]
  wire  wt15_io_Cout_9; // @[MulModule.scala 125:22]
  wire  wt15_io_Cout_10; // @[MulModule.scala 125:22]
  wire  wt15_io_Cout_11; // @[MulModule.scala 125:22]
  wire  wt15_io_Cout_12; // @[MulModule.scala 125:22]
  wire  wt15_io_Cout_13; // @[MulModule.scala 125:22]
  wire  wt15_io_Cout_14; // @[MulModule.scala 125:22]
  wire [15:0] wt16_io_N; // @[MulModule.scala 126:22]
  wire  wt16_io_S; // @[MulModule.scala 126:22]
  wire  wt16_io_C; // @[MulModule.scala 126:22]
  wire  wt16_io_Cin_0; // @[MulModule.scala 126:22]
  wire  wt16_io_Cin_1; // @[MulModule.scala 126:22]
  wire  wt16_io_Cin_2; // @[MulModule.scala 126:22]
  wire  wt16_io_Cin_3; // @[MulModule.scala 126:22]
  wire  wt16_io_Cin_4; // @[MulModule.scala 126:22]
  wire  wt16_io_Cin_5; // @[MulModule.scala 126:22]
  wire  wt16_io_Cin_6; // @[MulModule.scala 126:22]
  wire  wt16_io_Cin_7; // @[MulModule.scala 126:22]
  wire  wt16_io_Cin_8; // @[MulModule.scala 126:22]
  wire  wt16_io_Cin_9; // @[MulModule.scala 126:22]
  wire  wt16_io_Cin_10; // @[MulModule.scala 126:22]
  wire  wt16_io_Cin_11; // @[MulModule.scala 126:22]
  wire  wt16_io_Cin_12; // @[MulModule.scala 126:22]
  wire  wt16_io_Cin_13; // @[MulModule.scala 126:22]
  wire  wt16_io_Cin_14; // @[MulModule.scala 126:22]
  wire  wt16_io_Cout_0; // @[MulModule.scala 126:22]
  wire  wt16_io_Cout_1; // @[MulModule.scala 126:22]
  wire  wt16_io_Cout_2; // @[MulModule.scala 126:22]
  wire  wt16_io_Cout_3; // @[MulModule.scala 126:22]
  wire  wt16_io_Cout_4; // @[MulModule.scala 126:22]
  wire  wt16_io_Cout_5; // @[MulModule.scala 126:22]
  wire  wt16_io_Cout_6; // @[MulModule.scala 126:22]
  wire  wt16_io_Cout_7; // @[MulModule.scala 126:22]
  wire  wt16_io_Cout_8; // @[MulModule.scala 126:22]
  wire  wt16_io_Cout_9; // @[MulModule.scala 126:22]
  wire  wt16_io_Cout_10; // @[MulModule.scala 126:22]
  wire  wt16_io_Cout_11; // @[MulModule.scala 126:22]
  wire  wt16_io_Cout_12; // @[MulModule.scala 126:22]
  wire  wt16_io_Cout_13; // @[MulModule.scala 126:22]
  wire  wt16_io_Cout_14; // @[MulModule.scala 126:22]
  wire [15:0] wt17_io_N; // @[MulModule.scala 127:22]
  wire  wt17_io_S; // @[MulModule.scala 127:22]
  wire  wt17_io_C; // @[MulModule.scala 127:22]
  wire  wt17_io_Cin_0; // @[MulModule.scala 127:22]
  wire  wt17_io_Cin_1; // @[MulModule.scala 127:22]
  wire  wt17_io_Cin_2; // @[MulModule.scala 127:22]
  wire  wt17_io_Cin_3; // @[MulModule.scala 127:22]
  wire  wt17_io_Cin_4; // @[MulModule.scala 127:22]
  wire  wt17_io_Cin_5; // @[MulModule.scala 127:22]
  wire  wt17_io_Cin_6; // @[MulModule.scala 127:22]
  wire  wt17_io_Cin_7; // @[MulModule.scala 127:22]
  wire  wt17_io_Cin_8; // @[MulModule.scala 127:22]
  wire  wt17_io_Cin_9; // @[MulModule.scala 127:22]
  wire  wt17_io_Cin_10; // @[MulModule.scala 127:22]
  wire  wt17_io_Cin_11; // @[MulModule.scala 127:22]
  wire  wt17_io_Cin_12; // @[MulModule.scala 127:22]
  wire  wt17_io_Cin_13; // @[MulModule.scala 127:22]
  wire  wt17_io_Cin_14; // @[MulModule.scala 127:22]
  wire  wt17_io_Cout_0; // @[MulModule.scala 127:22]
  wire  wt17_io_Cout_1; // @[MulModule.scala 127:22]
  wire  wt17_io_Cout_2; // @[MulModule.scala 127:22]
  wire  wt17_io_Cout_3; // @[MulModule.scala 127:22]
  wire  wt17_io_Cout_4; // @[MulModule.scala 127:22]
  wire  wt17_io_Cout_5; // @[MulModule.scala 127:22]
  wire  wt17_io_Cout_6; // @[MulModule.scala 127:22]
  wire  wt17_io_Cout_7; // @[MulModule.scala 127:22]
  wire  wt17_io_Cout_8; // @[MulModule.scala 127:22]
  wire  wt17_io_Cout_9; // @[MulModule.scala 127:22]
  wire  wt17_io_Cout_10; // @[MulModule.scala 127:22]
  wire  wt17_io_Cout_11; // @[MulModule.scala 127:22]
  wire  wt17_io_Cout_12; // @[MulModule.scala 127:22]
  wire  wt17_io_Cout_13; // @[MulModule.scala 127:22]
  wire  wt17_io_Cout_14; // @[MulModule.scala 127:22]
  wire [15:0] wt18_io_N; // @[MulModule.scala 128:22]
  wire  wt18_io_S; // @[MulModule.scala 128:22]
  wire  wt18_io_C; // @[MulModule.scala 128:22]
  wire  wt18_io_Cin_0; // @[MulModule.scala 128:22]
  wire  wt18_io_Cin_1; // @[MulModule.scala 128:22]
  wire  wt18_io_Cin_2; // @[MulModule.scala 128:22]
  wire  wt18_io_Cin_3; // @[MulModule.scala 128:22]
  wire  wt18_io_Cin_4; // @[MulModule.scala 128:22]
  wire  wt18_io_Cin_5; // @[MulModule.scala 128:22]
  wire  wt18_io_Cin_6; // @[MulModule.scala 128:22]
  wire  wt18_io_Cin_7; // @[MulModule.scala 128:22]
  wire  wt18_io_Cin_8; // @[MulModule.scala 128:22]
  wire  wt18_io_Cin_9; // @[MulModule.scala 128:22]
  wire  wt18_io_Cin_10; // @[MulModule.scala 128:22]
  wire  wt18_io_Cin_11; // @[MulModule.scala 128:22]
  wire  wt18_io_Cin_12; // @[MulModule.scala 128:22]
  wire  wt18_io_Cin_13; // @[MulModule.scala 128:22]
  wire  wt18_io_Cin_14; // @[MulModule.scala 128:22]
  wire  wt18_io_Cout_0; // @[MulModule.scala 128:22]
  wire  wt18_io_Cout_1; // @[MulModule.scala 128:22]
  wire  wt18_io_Cout_2; // @[MulModule.scala 128:22]
  wire  wt18_io_Cout_3; // @[MulModule.scala 128:22]
  wire  wt18_io_Cout_4; // @[MulModule.scala 128:22]
  wire  wt18_io_Cout_5; // @[MulModule.scala 128:22]
  wire  wt18_io_Cout_6; // @[MulModule.scala 128:22]
  wire  wt18_io_Cout_7; // @[MulModule.scala 128:22]
  wire  wt18_io_Cout_8; // @[MulModule.scala 128:22]
  wire  wt18_io_Cout_9; // @[MulModule.scala 128:22]
  wire  wt18_io_Cout_10; // @[MulModule.scala 128:22]
  wire  wt18_io_Cout_11; // @[MulModule.scala 128:22]
  wire  wt18_io_Cout_12; // @[MulModule.scala 128:22]
  wire  wt18_io_Cout_13; // @[MulModule.scala 128:22]
  wire  wt18_io_Cout_14; // @[MulModule.scala 128:22]
  wire [15:0] wt19_io_N; // @[MulModule.scala 129:22]
  wire  wt19_io_S; // @[MulModule.scala 129:22]
  wire  wt19_io_C; // @[MulModule.scala 129:22]
  wire  wt19_io_Cin_0; // @[MulModule.scala 129:22]
  wire  wt19_io_Cin_1; // @[MulModule.scala 129:22]
  wire  wt19_io_Cin_2; // @[MulModule.scala 129:22]
  wire  wt19_io_Cin_3; // @[MulModule.scala 129:22]
  wire  wt19_io_Cin_4; // @[MulModule.scala 129:22]
  wire  wt19_io_Cin_5; // @[MulModule.scala 129:22]
  wire  wt19_io_Cin_6; // @[MulModule.scala 129:22]
  wire  wt19_io_Cin_7; // @[MulModule.scala 129:22]
  wire  wt19_io_Cin_8; // @[MulModule.scala 129:22]
  wire  wt19_io_Cin_9; // @[MulModule.scala 129:22]
  wire  wt19_io_Cin_10; // @[MulModule.scala 129:22]
  wire  wt19_io_Cin_11; // @[MulModule.scala 129:22]
  wire  wt19_io_Cin_12; // @[MulModule.scala 129:22]
  wire  wt19_io_Cin_13; // @[MulModule.scala 129:22]
  wire  wt19_io_Cin_14; // @[MulModule.scala 129:22]
  wire  wt19_io_Cout_0; // @[MulModule.scala 129:22]
  wire  wt19_io_Cout_1; // @[MulModule.scala 129:22]
  wire  wt19_io_Cout_2; // @[MulModule.scala 129:22]
  wire  wt19_io_Cout_3; // @[MulModule.scala 129:22]
  wire  wt19_io_Cout_4; // @[MulModule.scala 129:22]
  wire  wt19_io_Cout_5; // @[MulModule.scala 129:22]
  wire  wt19_io_Cout_6; // @[MulModule.scala 129:22]
  wire  wt19_io_Cout_7; // @[MulModule.scala 129:22]
  wire  wt19_io_Cout_8; // @[MulModule.scala 129:22]
  wire  wt19_io_Cout_9; // @[MulModule.scala 129:22]
  wire  wt19_io_Cout_10; // @[MulModule.scala 129:22]
  wire  wt19_io_Cout_11; // @[MulModule.scala 129:22]
  wire  wt19_io_Cout_12; // @[MulModule.scala 129:22]
  wire  wt19_io_Cout_13; // @[MulModule.scala 129:22]
  wire  wt19_io_Cout_14; // @[MulModule.scala 129:22]
  wire [15:0] wt20_io_N; // @[MulModule.scala 130:22]
  wire  wt20_io_S; // @[MulModule.scala 130:22]
  wire  wt20_io_C; // @[MulModule.scala 130:22]
  wire  wt20_io_Cin_0; // @[MulModule.scala 130:22]
  wire  wt20_io_Cin_1; // @[MulModule.scala 130:22]
  wire  wt20_io_Cin_2; // @[MulModule.scala 130:22]
  wire  wt20_io_Cin_3; // @[MulModule.scala 130:22]
  wire  wt20_io_Cin_4; // @[MulModule.scala 130:22]
  wire  wt20_io_Cin_5; // @[MulModule.scala 130:22]
  wire  wt20_io_Cin_6; // @[MulModule.scala 130:22]
  wire  wt20_io_Cin_7; // @[MulModule.scala 130:22]
  wire  wt20_io_Cin_8; // @[MulModule.scala 130:22]
  wire  wt20_io_Cin_9; // @[MulModule.scala 130:22]
  wire  wt20_io_Cin_10; // @[MulModule.scala 130:22]
  wire  wt20_io_Cin_11; // @[MulModule.scala 130:22]
  wire  wt20_io_Cin_12; // @[MulModule.scala 130:22]
  wire  wt20_io_Cin_13; // @[MulModule.scala 130:22]
  wire  wt20_io_Cin_14; // @[MulModule.scala 130:22]
  wire  wt20_io_Cout_0; // @[MulModule.scala 130:22]
  wire  wt20_io_Cout_1; // @[MulModule.scala 130:22]
  wire  wt20_io_Cout_2; // @[MulModule.scala 130:22]
  wire  wt20_io_Cout_3; // @[MulModule.scala 130:22]
  wire  wt20_io_Cout_4; // @[MulModule.scala 130:22]
  wire  wt20_io_Cout_5; // @[MulModule.scala 130:22]
  wire  wt20_io_Cout_6; // @[MulModule.scala 130:22]
  wire  wt20_io_Cout_7; // @[MulModule.scala 130:22]
  wire  wt20_io_Cout_8; // @[MulModule.scala 130:22]
  wire  wt20_io_Cout_9; // @[MulModule.scala 130:22]
  wire  wt20_io_Cout_10; // @[MulModule.scala 130:22]
  wire  wt20_io_Cout_11; // @[MulModule.scala 130:22]
  wire  wt20_io_Cout_12; // @[MulModule.scala 130:22]
  wire  wt20_io_Cout_13; // @[MulModule.scala 130:22]
  wire  wt20_io_Cout_14; // @[MulModule.scala 130:22]
  wire [15:0] wt21_io_N; // @[MulModule.scala 131:22]
  wire  wt21_io_S; // @[MulModule.scala 131:22]
  wire  wt21_io_C; // @[MulModule.scala 131:22]
  wire  wt21_io_Cin_0; // @[MulModule.scala 131:22]
  wire  wt21_io_Cin_1; // @[MulModule.scala 131:22]
  wire  wt21_io_Cin_2; // @[MulModule.scala 131:22]
  wire  wt21_io_Cin_3; // @[MulModule.scala 131:22]
  wire  wt21_io_Cin_4; // @[MulModule.scala 131:22]
  wire  wt21_io_Cin_5; // @[MulModule.scala 131:22]
  wire  wt21_io_Cin_6; // @[MulModule.scala 131:22]
  wire  wt21_io_Cin_7; // @[MulModule.scala 131:22]
  wire  wt21_io_Cin_8; // @[MulModule.scala 131:22]
  wire  wt21_io_Cin_9; // @[MulModule.scala 131:22]
  wire  wt21_io_Cin_10; // @[MulModule.scala 131:22]
  wire  wt21_io_Cin_11; // @[MulModule.scala 131:22]
  wire  wt21_io_Cin_12; // @[MulModule.scala 131:22]
  wire  wt21_io_Cin_13; // @[MulModule.scala 131:22]
  wire  wt21_io_Cin_14; // @[MulModule.scala 131:22]
  wire  wt21_io_Cout_0; // @[MulModule.scala 131:22]
  wire  wt21_io_Cout_1; // @[MulModule.scala 131:22]
  wire  wt21_io_Cout_2; // @[MulModule.scala 131:22]
  wire  wt21_io_Cout_3; // @[MulModule.scala 131:22]
  wire  wt21_io_Cout_4; // @[MulModule.scala 131:22]
  wire  wt21_io_Cout_5; // @[MulModule.scala 131:22]
  wire  wt21_io_Cout_6; // @[MulModule.scala 131:22]
  wire  wt21_io_Cout_7; // @[MulModule.scala 131:22]
  wire  wt21_io_Cout_8; // @[MulModule.scala 131:22]
  wire  wt21_io_Cout_9; // @[MulModule.scala 131:22]
  wire  wt21_io_Cout_10; // @[MulModule.scala 131:22]
  wire  wt21_io_Cout_11; // @[MulModule.scala 131:22]
  wire  wt21_io_Cout_12; // @[MulModule.scala 131:22]
  wire  wt21_io_Cout_13; // @[MulModule.scala 131:22]
  wire  wt21_io_Cout_14; // @[MulModule.scala 131:22]
  wire [15:0] wt22_io_N; // @[MulModule.scala 132:22]
  wire  wt22_io_S; // @[MulModule.scala 132:22]
  wire  wt22_io_C; // @[MulModule.scala 132:22]
  wire  wt22_io_Cin_0; // @[MulModule.scala 132:22]
  wire  wt22_io_Cin_1; // @[MulModule.scala 132:22]
  wire  wt22_io_Cin_2; // @[MulModule.scala 132:22]
  wire  wt22_io_Cin_3; // @[MulModule.scala 132:22]
  wire  wt22_io_Cin_4; // @[MulModule.scala 132:22]
  wire  wt22_io_Cin_5; // @[MulModule.scala 132:22]
  wire  wt22_io_Cin_6; // @[MulModule.scala 132:22]
  wire  wt22_io_Cin_7; // @[MulModule.scala 132:22]
  wire  wt22_io_Cin_8; // @[MulModule.scala 132:22]
  wire  wt22_io_Cin_9; // @[MulModule.scala 132:22]
  wire  wt22_io_Cin_10; // @[MulModule.scala 132:22]
  wire  wt22_io_Cin_11; // @[MulModule.scala 132:22]
  wire  wt22_io_Cin_12; // @[MulModule.scala 132:22]
  wire  wt22_io_Cin_13; // @[MulModule.scala 132:22]
  wire  wt22_io_Cin_14; // @[MulModule.scala 132:22]
  wire  wt22_io_Cout_0; // @[MulModule.scala 132:22]
  wire  wt22_io_Cout_1; // @[MulModule.scala 132:22]
  wire  wt22_io_Cout_2; // @[MulModule.scala 132:22]
  wire  wt22_io_Cout_3; // @[MulModule.scala 132:22]
  wire  wt22_io_Cout_4; // @[MulModule.scala 132:22]
  wire  wt22_io_Cout_5; // @[MulModule.scala 132:22]
  wire  wt22_io_Cout_6; // @[MulModule.scala 132:22]
  wire  wt22_io_Cout_7; // @[MulModule.scala 132:22]
  wire  wt22_io_Cout_8; // @[MulModule.scala 132:22]
  wire  wt22_io_Cout_9; // @[MulModule.scala 132:22]
  wire  wt22_io_Cout_10; // @[MulModule.scala 132:22]
  wire  wt22_io_Cout_11; // @[MulModule.scala 132:22]
  wire  wt22_io_Cout_12; // @[MulModule.scala 132:22]
  wire  wt22_io_Cout_13; // @[MulModule.scala 132:22]
  wire  wt22_io_Cout_14; // @[MulModule.scala 132:22]
  wire [15:0] wt23_io_N; // @[MulModule.scala 133:22]
  wire  wt23_io_S; // @[MulModule.scala 133:22]
  wire  wt23_io_C; // @[MulModule.scala 133:22]
  wire  wt23_io_Cin_0; // @[MulModule.scala 133:22]
  wire  wt23_io_Cin_1; // @[MulModule.scala 133:22]
  wire  wt23_io_Cin_2; // @[MulModule.scala 133:22]
  wire  wt23_io_Cin_3; // @[MulModule.scala 133:22]
  wire  wt23_io_Cin_4; // @[MulModule.scala 133:22]
  wire  wt23_io_Cin_5; // @[MulModule.scala 133:22]
  wire  wt23_io_Cin_6; // @[MulModule.scala 133:22]
  wire  wt23_io_Cin_7; // @[MulModule.scala 133:22]
  wire  wt23_io_Cin_8; // @[MulModule.scala 133:22]
  wire  wt23_io_Cin_9; // @[MulModule.scala 133:22]
  wire  wt23_io_Cin_10; // @[MulModule.scala 133:22]
  wire  wt23_io_Cin_11; // @[MulModule.scala 133:22]
  wire  wt23_io_Cin_12; // @[MulModule.scala 133:22]
  wire  wt23_io_Cin_13; // @[MulModule.scala 133:22]
  wire  wt23_io_Cin_14; // @[MulModule.scala 133:22]
  wire  wt23_io_Cout_0; // @[MulModule.scala 133:22]
  wire  wt23_io_Cout_1; // @[MulModule.scala 133:22]
  wire  wt23_io_Cout_2; // @[MulModule.scala 133:22]
  wire  wt23_io_Cout_3; // @[MulModule.scala 133:22]
  wire  wt23_io_Cout_4; // @[MulModule.scala 133:22]
  wire  wt23_io_Cout_5; // @[MulModule.scala 133:22]
  wire  wt23_io_Cout_6; // @[MulModule.scala 133:22]
  wire  wt23_io_Cout_7; // @[MulModule.scala 133:22]
  wire  wt23_io_Cout_8; // @[MulModule.scala 133:22]
  wire  wt23_io_Cout_9; // @[MulModule.scala 133:22]
  wire  wt23_io_Cout_10; // @[MulModule.scala 133:22]
  wire  wt23_io_Cout_11; // @[MulModule.scala 133:22]
  wire  wt23_io_Cout_12; // @[MulModule.scala 133:22]
  wire  wt23_io_Cout_13; // @[MulModule.scala 133:22]
  wire  wt23_io_Cout_14; // @[MulModule.scala 133:22]
  wire [15:0] wt24_io_N; // @[MulModule.scala 134:22]
  wire  wt24_io_S; // @[MulModule.scala 134:22]
  wire  wt24_io_C; // @[MulModule.scala 134:22]
  wire  wt24_io_Cin_0; // @[MulModule.scala 134:22]
  wire  wt24_io_Cin_1; // @[MulModule.scala 134:22]
  wire  wt24_io_Cin_2; // @[MulModule.scala 134:22]
  wire  wt24_io_Cin_3; // @[MulModule.scala 134:22]
  wire  wt24_io_Cin_4; // @[MulModule.scala 134:22]
  wire  wt24_io_Cin_5; // @[MulModule.scala 134:22]
  wire  wt24_io_Cin_6; // @[MulModule.scala 134:22]
  wire  wt24_io_Cin_7; // @[MulModule.scala 134:22]
  wire  wt24_io_Cin_8; // @[MulModule.scala 134:22]
  wire  wt24_io_Cin_9; // @[MulModule.scala 134:22]
  wire  wt24_io_Cin_10; // @[MulModule.scala 134:22]
  wire  wt24_io_Cin_11; // @[MulModule.scala 134:22]
  wire  wt24_io_Cin_12; // @[MulModule.scala 134:22]
  wire  wt24_io_Cin_13; // @[MulModule.scala 134:22]
  wire  wt24_io_Cin_14; // @[MulModule.scala 134:22]
  wire  wt24_io_Cout_0; // @[MulModule.scala 134:22]
  wire  wt24_io_Cout_1; // @[MulModule.scala 134:22]
  wire  wt24_io_Cout_2; // @[MulModule.scala 134:22]
  wire  wt24_io_Cout_3; // @[MulModule.scala 134:22]
  wire  wt24_io_Cout_4; // @[MulModule.scala 134:22]
  wire  wt24_io_Cout_5; // @[MulModule.scala 134:22]
  wire  wt24_io_Cout_6; // @[MulModule.scala 134:22]
  wire  wt24_io_Cout_7; // @[MulModule.scala 134:22]
  wire  wt24_io_Cout_8; // @[MulModule.scala 134:22]
  wire  wt24_io_Cout_9; // @[MulModule.scala 134:22]
  wire  wt24_io_Cout_10; // @[MulModule.scala 134:22]
  wire  wt24_io_Cout_11; // @[MulModule.scala 134:22]
  wire  wt24_io_Cout_12; // @[MulModule.scala 134:22]
  wire  wt24_io_Cout_13; // @[MulModule.scala 134:22]
  wire  wt24_io_Cout_14; // @[MulModule.scala 134:22]
  wire [15:0] wt25_io_N; // @[MulModule.scala 135:22]
  wire  wt25_io_S; // @[MulModule.scala 135:22]
  wire  wt25_io_C; // @[MulModule.scala 135:22]
  wire  wt25_io_Cin_0; // @[MulModule.scala 135:22]
  wire  wt25_io_Cin_1; // @[MulModule.scala 135:22]
  wire  wt25_io_Cin_2; // @[MulModule.scala 135:22]
  wire  wt25_io_Cin_3; // @[MulModule.scala 135:22]
  wire  wt25_io_Cin_4; // @[MulModule.scala 135:22]
  wire  wt25_io_Cin_5; // @[MulModule.scala 135:22]
  wire  wt25_io_Cin_6; // @[MulModule.scala 135:22]
  wire  wt25_io_Cin_7; // @[MulModule.scala 135:22]
  wire  wt25_io_Cin_8; // @[MulModule.scala 135:22]
  wire  wt25_io_Cin_9; // @[MulModule.scala 135:22]
  wire  wt25_io_Cin_10; // @[MulModule.scala 135:22]
  wire  wt25_io_Cin_11; // @[MulModule.scala 135:22]
  wire  wt25_io_Cin_12; // @[MulModule.scala 135:22]
  wire  wt25_io_Cin_13; // @[MulModule.scala 135:22]
  wire  wt25_io_Cin_14; // @[MulModule.scala 135:22]
  wire  wt25_io_Cout_0; // @[MulModule.scala 135:22]
  wire  wt25_io_Cout_1; // @[MulModule.scala 135:22]
  wire  wt25_io_Cout_2; // @[MulModule.scala 135:22]
  wire  wt25_io_Cout_3; // @[MulModule.scala 135:22]
  wire  wt25_io_Cout_4; // @[MulModule.scala 135:22]
  wire  wt25_io_Cout_5; // @[MulModule.scala 135:22]
  wire  wt25_io_Cout_6; // @[MulModule.scala 135:22]
  wire  wt25_io_Cout_7; // @[MulModule.scala 135:22]
  wire  wt25_io_Cout_8; // @[MulModule.scala 135:22]
  wire  wt25_io_Cout_9; // @[MulModule.scala 135:22]
  wire  wt25_io_Cout_10; // @[MulModule.scala 135:22]
  wire  wt25_io_Cout_11; // @[MulModule.scala 135:22]
  wire  wt25_io_Cout_12; // @[MulModule.scala 135:22]
  wire  wt25_io_Cout_13; // @[MulModule.scala 135:22]
  wire  wt25_io_Cout_14; // @[MulModule.scala 135:22]
  wire [15:0] wt26_io_N; // @[MulModule.scala 136:22]
  wire  wt26_io_S; // @[MulModule.scala 136:22]
  wire  wt26_io_C; // @[MulModule.scala 136:22]
  wire  wt26_io_Cin_0; // @[MulModule.scala 136:22]
  wire  wt26_io_Cin_1; // @[MulModule.scala 136:22]
  wire  wt26_io_Cin_2; // @[MulModule.scala 136:22]
  wire  wt26_io_Cin_3; // @[MulModule.scala 136:22]
  wire  wt26_io_Cin_4; // @[MulModule.scala 136:22]
  wire  wt26_io_Cin_5; // @[MulModule.scala 136:22]
  wire  wt26_io_Cin_6; // @[MulModule.scala 136:22]
  wire  wt26_io_Cin_7; // @[MulModule.scala 136:22]
  wire  wt26_io_Cin_8; // @[MulModule.scala 136:22]
  wire  wt26_io_Cin_9; // @[MulModule.scala 136:22]
  wire  wt26_io_Cin_10; // @[MulModule.scala 136:22]
  wire  wt26_io_Cin_11; // @[MulModule.scala 136:22]
  wire  wt26_io_Cin_12; // @[MulModule.scala 136:22]
  wire  wt26_io_Cin_13; // @[MulModule.scala 136:22]
  wire  wt26_io_Cin_14; // @[MulModule.scala 136:22]
  wire  wt26_io_Cout_0; // @[MulModule.scala 136:22]
  wire  wt26_io_Cout_1; // @[MulModule.scala 136:22]
  wire  wt26_io_Cout_2; // @[MulModule.scala 136:22]
  wire  wt26_io_Cout_3; // @[MulModule.scala 136:22]
  wire  wt26_io_Cout_4; // @[MulModule.scala 136:22]
  wire  wt26_io_Cout_5; // @[MulModule.scala 136:22]
  wire  wt26_io_Cout_6; // @[MulModule.scala 136:22]
  wire  wt26_io_Cout_7; // @[MulModule.scala 136:22]
  wire  wt26_io_Cout_8; // @[MulModule.scala 136:22]
  wire  wt26_io_Cout_9; // @[MulModule.scala 136:22]
  wire  wt26_io_Cout_10; // @[MulModule.scala 136:22]
  wire  wt26_io_Cout_11; // @[MulModule.scala 136:22]
  wire  wt26_io_Cout_12; // @[MulModule.scala 136:22]
  wire  wt26_io_Cout_13; // @[MulModule.scala 136:22]
  wire  wt26_io_Cout_14; // @[MulModule.scala 136:22]
  wire [15:0] wt27_io_N; // @[MulModule.scala 137:22]
  wire  wt27_io_S; // @[MulModule.scala 137:22]
  wire  wt27_io_C; // @[MulModule.scala 137:22]
  wire  wt27_io_Cin_0; // @[MulModule.scala 137:22]
  wire  wt27_io_Cin_1; // @[MulModule.scala 137:22]
  wire  wt27_io_Cin_2; // @[MulModule.scala 137:22]
  wire  wt27_io_Cin_3; // @[MulModule.scala 137:22]
  wire  wt27_io_Cin_4; // @[MulModule.scala 137:22]
  wire  wt27_io_Cin_5; // @[MulModule.scala 137:22]
  wire  wt27_io_Cin_6; // @[MulModule.scala 137:22]
  wire  wt27_io_Cin_7; // @[MulModule.scala 137:22]
  wire  wt27_io_Cin_8; // @[MulModule.scala 137:22]
  wire  wt27_io_Cin_9; // @[MulModule.scala 137:22]
  wire  wt27_io_Cin_10; // @[MulModule.scala 137:22]
  wire  wt27_io_Cin_11; // @[MulModule.scala 137:22]
  wire  wt27_io_Cin_12; // @[MulModule.scala 137:22]
  wire  wt27_io_Cin_13; // @[MulModule.scala 137:22]
  wire  wt27_io_Cin_14; // @[MulModule.scala 137:22]
  wire  wt27_io_Cout_0; // @[MulModule.scala 137:22]
  wire  wt27_io_Cout_1; // @[MulModule.scala 137:22]
  wire  wt27_io_Cout_2; // @[MulModule.scala 137:22]
  wire  wt27_io_Cout_3; // @[MulModule.scala 137:22]
  wire  wt27_io_Cout_4; // @[MulModule.scala 137:22]
  wire  wt27_io_Cout_5; // @[MulModule.scala 137:22]
  wire  wt27_io_Cout_6; // @[MulModule.scala 137:22]
  wire  wt27_io_Cout_7; // @[MulModule.scala 137:22]
  wire  wt27_io_Cout_8; // @[MulModule.scala 137:22]
  wire  wt27_io_Cout_9; // @[MulModule.scala 137:22]
  wire  wt27_io_Cout_10; // @[MulModule.scala 137:22]
  wire  wt27_io_Cout_11; // @[MulModule.scala 137:22]
  wire  wt27_io_Cout_12; // @[MulModule.scala 137:22]
  wire  wt27_io_Cout_13; // @[MulModule.scala 137:22]
  wire  wt27_io_Cout_14; // @[MulModule.scala 137:22]
  wire [15:0] wt28_io_N; // @[MulModule.scala 138:22]
  wire  wt28_io_S; // @[MulModule.scala 138:22]
  wire  wt28_io_C; // @[MulModule.scala 138:22]
  wire  wt28_io_Cin_0; // @[MulModule.scala 138:22]
  wire  wt28_io_Cin_1; // @[MulModule.scala 138:22]
  wire  wt28_io_Cin_2; // @[MulModule.scala 138:22]
  wire  wt28_io_Cin_3; // @[MulModule.scala 138:22]
  wire  wt28_io_Cin_4; // @[MulModule.scala 138:22]
  wire  wt28_io_Cin_5; // @[MulModule.scala 138:22]
  wire  wt28_io_Cin_6; // @[MulModule.scala 138:22]
  wire  wt28_io_Cin_7; // @[MulModule.scala 138:22]
  wire  wt28_io_Cin_8; // @[MulModule.scala 138:22]
  wire  wt28_io_Cin_9; // @[MulModule.scala 138:22]
  wire  wt28_io_Cin_10; // @[MulModule.scala 138:22]
  wire  wt28_io_Cin_11; // @[MulModule.scala 138:22]
  wire  wt28_io_Cin_12; // @[MulModule.scala 138:22]
  wire  wt28_io_Cin_13; // @[MulModule.scala 138:22]
  wire  wt28_io_Cin_14; // @[MulModule.scala 138:22]
  wire  wt28_io_Cout_0; // @[MulModule.scala 138:22]
  wire  wt28_io_Cout_1; // @[MulModule.scala 138:22]
  wire  wt28_io_Cout_2; // @[MulModule.scala 138:22]
  wire  wt28_io_Cout_3; // @[MulModule.scala 138:22]
  wire  wt28_io_Cout_4; // @[MulModule.scala 138:22]
  wire  wt28_io_Cout_5; // @[MulModule.scala 138:22]
  wire  wt28_io_Cout_6; // @[MulModule.scala 138:22]
  wire  wt28_io_Cout_7; // @[MulModule.scala 138:22]
  wire  wt28_io_Cout_8; // @[MulModule.scala 138:22]
  wire  wt28_io_Cout_9; // @[MulModule.scala 138:22]
  wire  wt28_io_Cout_10; // @[MulModule.scala 138:22]
  wire  wt28_io_Cout_11; // @[MulModule.scala 138:22]
  wire  wt28_io_Cout_12; // @[MulModule.scala 138:22]
  wire  wt28_io_Cout_13; // @[MulModule.scala 138:22]
  wire  wt28_io_Cout_14; // @[MulModule.scala 138:22]
  wire [15:0] wt29_io_N; // @[MulModule.scala 139:22]
  wire  wt29_io_S; // @[MulModule.scala 139:22]
  wire  wt29_io_C; // @[MulModule.scala 139:22]
  wire  wt29_io_Cin_0; // @[MulModule.scala 139:22]
  wire  wt29_io_Cin_1; // @[MulModule.scala 139:22]
  wire  wt29_io_Cin_2; // @[MulModule.scala 139:22]
  wire  wt29_io_Cin_3; // @[MulModule.scala 139:22]
  wire  wt29_io_Cin_4; // @[MulModule.scala 139:22]
  wire  wt29_io_Cin_5; // @[MulModule.scala 139:22]
  wire  wt29_io_Cin_6; // @[MulModule.scala 139:22]
  wire  wt29_io_Cin_7; // @[MulModule.scala 139:22]
  wire  wt29_io_Cin_8; // @[MulModule.scala 139:22]
  wire  wt29_io_Cin_9; // @[MulModule.scala 139:22]
  wire  wt29_io_Cin_10; // @[MulModule.scala 139:22]
  wire  wt29_io_Cin_11; // @[MulModule.scala 139:22]
  wire  wt29_io_Cin_12; // @[MulModule.scala 139:22]
  wire  wt29_io_Cin_13; // @[MulModule.scala 139:22]
  wire  wt29_io_Cin_14; // @[MulModule.scala 139:22]
  wire  wt29_io_Cout_0; // @[MulModule.scala 139:22]
  wire  wt29_io_Cout_1; // @[MulModule.scala 139:22]
  wire  wt29_io_Cout_2; // @[MulModule.scala 139:22]
  wire  wt29_io_Cout_3; // @[MulModule.scala 139:22]
  wire  wt29_io_Cout_4; // @[MulModule.scala 139:22]
  wire  wt29_io_Cout_5; // @[MulModule.scala 139:22]
  wire  wt29_io_Cout_6; // @[MulModule.scala 139:22]
  wire  wt29_io_Cout_7; // @[MulModule.scala 139:22]
  wire  wt29_io_Cout_8; // @[MulModule.scala 139:22]
  wire  wt29_io_Cout_9; // @[MulModule.scala 139:22]
  wire  wt29_io_Cout_10; // @[MulModule.scala 139:22]
  wire  wt29_io_Cout_11; // @[MulModule.scala 139:22]
  wire  wt29_io_Cout_12; // @[MulModule.scala 139:22]
  wire  wt29_io_Cout_13; // @[MulModule.scala 139:22]
  wire  wt29_io_Cout_14; // @[MulModule.scala 139:22]
  wire [15:0] wt30_io_N; // @[MulModule.scala 140:22]
  wire  wt30_io_S; // @[MulModule.scala 140:22]
  wire  wt30_io_C; // @[MulModule.scala 140:22]
  wire  wt30_io_Cin_0; // @[MulModule.scala 140:22]
  wire  wt30_io_Cin_1; // @[MulModule.scala 140:22]
  wire  wt30_io_Cin_2; // @[MulModule.scala 140:22]
  wire  wt30_io_Cin_3; // @[MulModule.scala 140:22]
  wire  wt30_io_Cin_4; // @[MulModule.scala 140:22]
  wire  wt30_io_Cin_5; // @[MulModule.scala 140:22]
  wire  wt30_io_Cin_6; // @[MulModule.scala 140:22]
  wire  wt30_io_Cin_7; // @[MulModule.scala 140:22]
  wire  wt30_io_Cin_8; // @[MulModule.scala 140:22]
  wire  wt30_io_Cin_9; // @[MulModule.scala 140:22]
  wire  wt30_io_Cin_10; // @[MulModule.scala 140:22]
  wire  wt30_io_Cin_11; // @[MulModule.scala 140:22]
  wire  wt30_io_Cin_12; // @[MulModule.scala 140:22]
  wire  wt30_io_Cin_13; // @[MulModule.scala 140:22]
  wire  wt30_io_Cin_14; // @[MulModule.scala 140:22]
  wire  wt30_io_Cout_0; // @[MulModule.scala 140:22]
  wire  wt30_io_Cout_1; // @[MulModule.scala 140:22]
  wire  wt30_io_Cout_2; // @[MulModule.scala 140:22]
  wire  wt30_io_Cout_3; // @[MulModule.scala 140:22]
  wire  wt30_io_Cout_4; // @[MulModule.scala 140:22]
  wire  wt30_io_Cout_5; // @[MulModule.scala 140:22]
  wire  wt30_io_Cout_6; // @[MulModule.scala 140:22]
  wire  wt30_io_Cout_7; // @[MulModule.scala 140:22]
  wire  wt30_io_Cout_8; // @[MulModule.scala 140:22]
  wire  wt30_io_Cout_9; // @[MulModule.scala 140:22]
  wire  wt30_io_Cout_10; // @[MulModule.scala 140:22]
  wire  wt30_io_Cout_11; // @[MulModule.scala 140:22]
  wire  wt30_io_Cout_12; // @[MulModule.scala 140:22]
  wire  wt30_io_Cout_13; // @[MulModule.scala 140:22]
  wire  wt30_io_Cout_14; // @[MulModule.scala 140:22]
  wire [15:0] wt31_io_N; // @[MulModule.scala 141:22]
  wire  wt31_io_S; // @[MulModule.scala 141:22]
  wire  wt31_io_C; // @[MulModule.scala 141:22]
  wire  wt31_io_Cin_0; // @[MulModule.scala 141:22]
  wire  wt31_io_Cin_1; // @[MulModule.scala 141:22]
  wire  wt31_io_Cin_2; // @[MulModule.scala 141:22]
  wire  wt31_io_Cin_3; // @[MulModule.scala 141:22]
  wire  wt31_io_Cin_4; // @[MulModule.scala 141:22]
  wire  wt31_io_Cin_5; // @[MulModule.scala 141:22]
  wire  wt31_io_Cin_6; // @[MulModule.scala 141:22]
  wire  wt31_io_Cin_7; // @[MulModule.scala 141:22]
  wire  wt31_io_Cin_8; // @[MulModule.scala 141:22]
  wire  wt31_io_Cin_9; // @[MulModule.scala 141:22]
  wire  wt31_io_Cin_10; // @[MulModule.scala 141:22]
  wire  wt31_io_Cin_11; // @[MulModule.scala 141:22]
  wire  wt31_io_Cin_12; // @[MulModule.scala 141:22]
  wire  wt31_io_Cin_13; // @[MulModule.scala 141:22]
  wire  wt31_io_Cin_14; // @[MulModule.scala 141:22]
  wire  wt31_io_Cout_0; // @[MulModule.scala 141:22]
  wire  wt31_io_Cout_1; // @[MulModule.scala 141:22]
  wire  wt31_io_Cout_2; // @[MulModule.scala 141:22]
  wire  wt31_io_Cout_3; // @[MulModule.scala 141:22]
  wire  wt31_io_Cout_4; // @[MulModule.scala 141:22]
  wire  wt31_io_Cout_5; // @[MulModule.scala 141:22]
  wire  wt31_io_Cout_6; // @[MulModule.scala 141:22]
  wire  wt31_io_Cout_7; // @[MulModule.scala 141:22]
  wire  wt31_io_Cout_8; // @[MulModule.scala 141:22]
  wire  wt31_io_Cout_9; // @[MulModule.scala 141:22]
  wire  wt31_io_Cout_10; // @[MulModule.scala 141:22]
  wire  wt31_io_Cout_11; // @[MulModule.scala 141:22]
  wire  wt31_io_Cout_12; // @[MulModule.scala 141:22]
  wire  wt31_io_Cout_13; // @[MulModule.scala 141:22]
  wire  wt31_io_Cout_14; // @[MulModule.scala 141:22]
  wire [1:0] bc0_io_y_hi = io_OpB[1:0]; // @[MulModule.scala 35:27]
  wire [33:0] _bc1_io_X_T = {io_OpA, 2'h0}; // @[MulModule.scala 36:25]
  wire [35:0] _bc2_io_X_T = {io_OpA, 4'h0}; // @[MulModule.scala 38:25]
  wire [37:0] _bc3_io_X_T = {io_OpA, 6'h0}; // @[MulModule.scala 40:25]
  wire [39:0] _bc4_io_X_T = {io_OpA, 8'h0}; // @[MulModule.scala 42:25]
  wire [41:0] _bc5_io_X_T = {io_OpA, 10'h0}; // @[MulModule.scala 44:25]
  wire [43:0] _bc6_io_X_T = {io_OpA, 12'h0}; // @[MulModule.scala 46:25]
  wire [45:0] _bc7_io_X_T = {io_OpA, 14'h0}; // @[MulModule.scala 48:25]
  wire [47:0] _bc8_io_X_T = {io_OpA, 16'h0}; // @[MulModule.scala 50:25]
  wire [49:0] _bc9_io_X_T = {io_OpA, 18'h0}; // @[MulModule.scala 52:25]
  wire [51:0] _bc10_io_X_T = {io_OpA, 20'h0}; // @[MulModule.scala 54:26]
  wire [53:0] _bc11_io_X_T = {io_OpA, 22'h0}; // @[MulModule.scala 56:26]
  wire [55:0] _bc12_io_X_T = {io_OpA, 24'h0}; // @[MulModule.scala 58:26]
  wire [57:0] _bc13_io_X_T = {io_OpA, 26'h0}; // @[MulModule.scala 60:26]
  wire [59:0] _bc14_io_X_T = {io_OpA, 28'h0}; // @[MulModule.scala 62:26]
  wire [61:0] _bc15_io_X_T = {io_OpA, 30'h0}; // @[MulModule.scala 64:26]
  reg [31:0] PsReg_0; // @[MulModule.scala 103:24]
  reg [31:0] PsReg_1; // @[MulModule.scala 103:24]
  reg [31:0] PsReg_2; // @[MulModule.scala 103:24]
  reg [31:0] PsReg_3; // @[MulModule.scala 103:24]
  reg [31:0] PsReg_4; // @[MulModule.scala 103:24]
  reg [31:0] PsReg_5; // @[MulModule.scala 103:24]
  reg [31:0] PsReg_6; // @[MulModule.scala 103:24]
  reg [31:0] PsReg_7; // @[MulModule.scala 103:24]
  reg [31:0] PsReg_8; // @[MulModule.scala 103:24]
  reg [31:0] PsReg_9; // @[MulModule.scala 103:24]
  reg [31:0] PsReg_10; // @[MulModule.scala 103:24]
  reg [31:0] PsReg_11; // @[MulModule.scala 103:24]
  reg [31:0] PsReg_12; // @[MulModule.scala 103:24]
  reg [31:0] PsReg_13; // @[MulModule.scala 103:24]
  reg [31:0] PsReg_14; // @[MulModule.scala 103:24]
  reg [31:0] PsReg_15; // @[MulModule.scala 103:24]
  reg  csReg_0; // @[MulModule.scala 104:24]
  reg  csReg_1; // @[MulModule.scala 104:24]
  reg  csReg_2; // @[MulModule.scala 104:24]
  reg  csReg_3; // @[MulModule.scala 104:24]
  reg  csReg_4; // @[MulModule.scala 104:24]
  reg  csReg_5; // @[MulModule.scala 104:24]
  reg  csReg_6; // @[MulModule.scala 104:24]
  reg  csReg_7; // @[MulModule.scala 104:24]
  reg  csReg_8; // @[MulModule.scala 104:24]
  reg  csReg_9; // @[MulModule.scala 104:24]
  reg  csReg_10; // @[MulModule.scala 104:24]
  reg  csReg_11; // @[MulModule.scala 104:24]
  reg  csReg_12; // @[MulModule.scala 104:24]
  reg  csReg_13; // @[MulModule.scala 104:24]
  reg  csReg_14; // @[MulModule.scala 104:24]
  reg  csReg_15; // @[MulModule.scala 104:24]
  wire  Ns_0_0 = PsReg_0[0]; // @[MulModule.scala 146:33]
  wire  Ns_0_1 = PsReg_1[0]; // @[MulModule.scala 146:33]
  wire  Ns_0_2 = PsReg_2[0]; // @[MulModule.scala 146:33]
  wire  Ns_0_3 = PsReg_3[0]; // @[MulModule.scala 146:33]
  wire  Ns_0_4 = PsReg_4[0]; // @[MulModule.scala 146:33]
  wire  Ns_0_5 = PsReg_5[0]; // @[MulModule.scala 146:33]
  wire  Ns_0_6 = PsReg_6[0]; // @[MulModule.scala 146:33]
  wire  Ns_0_7 = PsReg_7[0]; // @[MulModule.scala 146:33]
  wire  Ns_0_8 = PsReg_8[0]; // @[MulModule.scala 146:33]
  wire  Ns_0_9 = PsReg_9[0]; // @[MulModule.scala 146:33]
  wire  Ns_0_10 = PsReg_10[0]; // @[MulModule.scala 146:33]
  wire  Ns_0_11 = PsReg_11[0]; // @[MulModule.scala 146:33]
  wire  Ns_0_12 = PsReg_12[0]; // @[MulModule.scala 146:33]
  wire  Ns_0_13 = PsReg_13[0]; // @[MulModule.scala 146:33]
  wire  Ns_0_14 = PsReg_14[0]; // @[MulModule.scala 146:33]
  wire  Ns_0_15 = PsReg_15[0]; // @[MulModule.scala 146:33]
  wire  Ns_1_0 = PsReg_0[1]; // @[MulModule.scala 146:33]
  wire  Ns_1_1 = PsReg_1[1]; // @[MulModule.scala 146:33]
  wire  Ns_1_2 = PsReg_2[1]; // @[MulModule.scala 146:33]
  wire  Ns_1_3 = PsReg_3[1]; // @[MulModule.scala 146:33]
  wire  Ns_1_4 = PsReg_4[1]; // @[MulModule.scala 146:33]
  wire  Ns_1_5 = PsReg_5[1]; // @[MulModule.scala 146:33]
  wire  Ns_1_6 = PsReg_6[1]; // @[MulModule.scala 146:33]
  wire  Ns_1_7 = PsReg_7[1]; // @[MulModule.scala 146:33]
  wire  Ns_1_8 = PsReg_8[1]; // @[MulModule.scala 146:33]
  wire  Ns_1_9 = PsReg_9[1]; // @[MulModule.scala 146:33]
  wire  Ns_1_10 = PsReg_10[1]; // @[MulModule.scala 146:33]
  wire  Ns_1_11 = PsReg_11[1]; // @[MulModule.scala 146:33]
  wire  Ns_1_12 = PsReg_12[1]; // @[MulModule.scala 146:33]
  wire  Ns_1_13 = PsReg_13[1]; // @[MulModule.scala 146:33]
  wire  Ns_1_14 = PsReg_14[1]; // @[MulModule.scala 146:33]
  wire  Ns_1_15 = PsReg_15[1]; // @[MulModule.scala 146:33]
  wire  Ns_2_0 = PsReg_0[2]; // @[MulModule.scala 146:33]
  wire  Ns_2_1 = PsReg_1[2]; // @[MulModule.scala 146:33]
  wire  Ns_2_2 = PsReg_2[2]; // @[MulModule.scala 146:33]
  wire  Ns_2_3 = PsReg_3[2]; // @[MulModule.scala 146:33]
  wire  Ns_2_4 = PsReg_4[2]; // @[MulModule.scala 146:33]
  wire  Ns_2_5 = PsReg_5[2]; // @[MulModule.scala 146:33]
  wire  Ns_2_6 = PsReg_6[2]; // @[MulModule.scala 146:33]
  wire  Ns_2_7 = PsReg_7[2]; // @[MulModule.scala 146:33]
  wire  Ns_2_8 = PsReg_8[2]; // @[MulModule.scala 146:33]
  wire  Ns_2_9 = PsReg_9[2]; // @[MulModule.scala 146:33]
  wire  Ns_2_10 = PsReg_10[2]; // @[MulModule.scala 146:33]
  wire  Ns_2_11 = PsReg_11[2]; // @[MulModule.scala 146:33]
  wire  Ns_2_12 = PsReg_12[2]; // @[MulModule.scala 146:33]
  wire  Ns_2_13 = PsReg_13[2]; // @[MulModule.scala 146:33]
  wire  Ns_2_14 = PsReg_14[2]; // @[MulModule.scala 146:33]
  wire  Ns_2_15 = PsReg_15[2]; // @[MulModule.scala 146:33]
  wire  Ns_3_0 = PsReg_0[3]; // @[MulModule.scala 146:33]
  wire  Ns_3_1 = PsReg_1[3]; // @[MulModule.scala 146:33]
  wire  Ns_3_2 = PsReg_2[3]; // @[MulModule.scala 146:33]
  wire  Ns_3_3 = PsReg_3[3]; // @[MulModule.scala 146:33]
  wire  Ns_3_4 = PsReg_4[3]; // @[MulModule.scala 146:33]
  wire  Ns_3_5 = PsReg_5[3]; // @[MulModule.scala 146:33]
  wire  Ns_3_6 = PsReg_6[3]; // @[MulModule.scala 146:33]
  wire  Ns_3_7 = PsReg_7[3]; // @[MulModule.scala 146:33]
  wire  Ns_3_8 = PsReg_8[3]; // @[MulModule.scala 146:33]
  wire  Ns_3_9 = PsReg_9[3]; // @[MulModule.scala 146:33]
  wire  Ns_3_10 = PsReg_10[3]; // @[MulModule.scala 146:33]
  wire  Ns_3_11 = PsReg_11[3]; // @[MulModule.scala 146:33]
  wire  Ns_3_12 = PsReg_12[3]; // @[MulModule.scala 146:33]
  wire  Ns_3_13 = PsReg_13[3]; // @[MulModule.scala 146:33]
  wire  Ns_3_14 = PsReg_14[3]; // @[MulModule.scala 146:33]
  wire  Ns_3_15 = PsReg_15[3]; // @[MulModule.scala 146:33]
  wire  Ns_4_0 = PsReg_0[4]; // @[MulModule.scala 146:33]
  wire  Ns_4_1 = PsReg_1[4]; // @[MulModule.scala 146:33]
  wire  Ns_4_2 = PsReg_2[4]; // @[MulModule.scala 146:33]
  wire  Ns_4_3 = PsReg_3[4]; // @[MulModule.scala 146:33]
  wire  Ns_4_4 = PsReg_4[4]; // @[MulModule.scala 146:33]
  wire  Ns_4_5 = PsReg_5[4]; // @[MulModule.scala 146:33]
  wire  Ns_4_6 = PsReg_6[4]; // @[MulModule.scala 146:33]
  wire  Ns_4_7 = PsReg_7[4]; // @[MulModule.scala 146:33]
  wire  Ns_4_8 = PsReg_8[4]; // @[MulModule.scala 146:33]
  wire  Ns_4_9 = PsReg_9[4]; // @[MulModule.scala 146:33]
  wire  Ns_4_10 = PsReg_10[4]; // @[MulModule.scala 146:33]
  wire  Ns_4_11 = PsReg_11[4]; // @[MulModule.scala 146:33]
  wire  Ns_4_12 = PsReg_12[4]; // @[MulModule.scala 146:33]
  wire  Ns_4_13 = PsReg_13[4]; // @[MulModule.scala 146:33]
  wire  Ns_4_14 = PsReg_14[4]; // @[MulModule.scala 146:33]
  wire  Ns_4_15 = PsReg_15[4]; // @[MulModule.scala 146:33]
  wire  Ns_5_0 = PsReg_0[5]; // @[MulModule.scala 146:33]
  wire  Ns_5_1 = PsReg_1[5]; // @[MulModule.scala 146:33]
  wire  Ns_5_2 = PsReg_2[5]; // @[MulModule.scala 146:33]
  wire  Ns_5_3 = PsReg_3[5]; // @[MulModule.scala 146:33]
  wire  Ns_5_4 = PsReg_4[5]; // @[MulModule.scala 146:33]
  wire  Ns_5_5 = PsReg_5[5]; // @[MulModule.scala 146:33]
  wire  Ns_5_6 = PsReg_6[5]; // @[MulModule.scala 146:33]
  wire  Ns_5_7 = PsReg_7[5]; // @[MulModule.scala 146:33]
  wire  Ns_5_8 = PsReg_8[5]; // @[MulModule.scala 146:33]
  wire  Ns_5_9 = PsReg_9[5]; // @[MulModule.scala 146:33]
  wire  Ns_5_10 = PsReg_10[5]; // @[MulModule.scala 146:33]
  wire  Ns_5_11 = PsReg_11[5]; // @[MulModule.scala 146:33]
  wire  Ns_5_12 = PsReg_12[5]; // @[MulModule.scala 146:33]
  wire  Ns_5_13 = PsReg_13[5]; // @[MulModule.scala 146:33]
  wire  Ns_5_14 = PsReg_14[5]; // @[MulModule.scala 146:33]
  wire  Ns_5_15 = PsReg_15[5]; // @[MulModule.scala 146:33]
  wire  Ns_6_0 = PsReg_0[6]; // @[MulModule.scala 146:33]
  wire  Ns_6_1 = PsReg_1[6]; // @[MulModule.scala 146:33]
  wire  Ns_6_2 = PsReg_2[6]; // @[MulModule.scala 146:33]
  wire  Ns_6_3 = PsReg_3[6]; // @[MulModule.scala 146:33]
  wire  Ns_6_4 = PsReg_4[6]; // @[MulModule.scala 146:33]
  wire  Ns_6_5 = PsReg_5[6]; // @[MulModule.scala 146:33]
  wire  Ns_6_6 = PsReg_6[6]; // @[MulModule.scala 146:33]
  wire  Ns_6_7 = PsReg_7[6]; // @[MulModule.scala 146:33]
  wire  Ns_6_8 = PsReg_8[6]; // @[MulModule.scala 146:33]
  wire  Ns_6_9 = PsReg_9[6]; // @[MulModule.scala 146:33]
  wire  Ns_6_10 = PsReg_10[6]; // @[MulModule.scala 146:33]
  wire  Ns_6_11 = PsReg_11[6]; // @[MulModule.scala 146:33]
  wire  Ns_6_12 = PsReg_12[6]; // @[MulModule.scala 146:33]
  wire  Ns_6_13 = PsReg_13[6]; // @[MulModule.scala 146:33]
  wire  Ns_6_14 = PsReg_14[6]; // @[MulModule.scala 146:33]
  wire  Ns_6_15 = PsReg_15[6]; // @[MulModule.scala 146:33]
  wire  Ns_7_0 = PsReg_0[7]; // @[MulModule.scala 146:33]
  wire  Ns_7_1 = PsReg_1[7]; // @[MulModule.scala 146:33]
  wire  Ns_7_2 = PsReg_2[7]; // @[MulModule.scala 146:33]
  wire  Ns_7_3 = PsReg_3[7]; // @[MulModule.scala 146:33]
  wire  Ns_7_4 = PsReg_4[7]; // @[MulModule.scala 146:33]
  wire  Ns_7_5 = PsReg_5[7]; // @[MulModule.scala 146:33]
  wire  Ns_7_6 = PsReg_6[7]; // @[MulModule.scala 146:33]
  wire  Ns_7_7 = PsReg_7[7]; // @[MulModule.scala 146:33]
  wire  Ns_7_8 = PsReg_8[7]; // @[MulModule.scala 146:33]
  wire  Ns_7_9 = PsReg_9[7]; // @[MulModule.scala 146:33]
  wire  Ns_7_10 = PsReg_10[7]; // @[MulModule.scala 146:33]
  wire  Ns_7_11 = PsReg_11[7]; // @[MulModule.scala 146:33]
  wire  Ns_7_12 = PsReg_12[7]; // @[MulModule.scala 146:33]
  wire  Ns_7_13 = PsReg_13[7]; // @[MulModule.scala 146:33]
  wire  Ns_7_14 = PsReg_14[7]; // @[MulModule.scala 146:33]
  wire  Ns_7_15 = PsReg_15[7]; // @[MulModule.scala 146:33]
  wire  Ns_8_0 = PsReg_0[8]; // @[MulModule.scala 146:33]
  wire  Ns_8_1 = PsReg_1[8]; // @[MulModule.scala 146:33]
  wire  Ns_8_2 = PsReg_2[8]; // @[MulModule.scala 146:33]
  wire  Ns_8_3 = PsReg_3[8]; // @[MulModule.scala 146:33]
  wire  Ns_8_4 = PsReg_4[8]; // @[MulModule.scala 146:33]
  wire  Ns_8_5 = PsReg_5[8]; // @[MulModule.scala 146:33]
  wire  Ns_8_6 = PsReg_6[8]; // @[MulModule.scala 146:33]
  wire  Ns_8_7 = PsReg_7[8]; // @[MulModule.scala 146:33]
  wire  Ns_8_8 = PsReg_8[8]; // @[MulModule.scala 146:33]
  wire  Ns_8_9 = PsReg_9[8]; // @[MulModule.scala 146:33]
  wire  Ns_8_10 = PsReg_10[8]; // @[MulModule.scala 146:33]
  wire  Ns_8_11 = PsReg_11[8]; // @[MulModule.scala 146:33]
  wire  Ns_8_12 = PsReg_12[8]; // @[MulModule.scala 146:33]
  wire  Ns_8_13 = PsReg_13[8]; // @[MulModule.scala 146:33]
  wire  Ns_8_14 = PsReg_14[8]; // @[MulModule.scala 146:33]
  wire  Ns_8_15 = PsReg_15[8]; // @[MulModule.scala 146:33]
  wire  Ns_9_0 = PsReg_0[9]; // @[MulModule.scala 146:33]
  wire  Ns_9_1 = PsReg_1[9]; // @[MulModule.scala 146:33]
  wire  Ns_9_2 = PsReg_2[9]; // @[MulModule.scala 146:33]
  wire  Ns_9_3 = PsReg_3[9]; // @[MulModule.scala 146:33]
  wire  Ns_9_4 = PsReg_4[9]; // @[MulModule.scala 146:33]
  wire  Ns_9_5 = PsReg_5[9]; // @[MulModule.scala 146:33]
  wire  Ns_9_6 = PsReg_6[9]; // @[MulModule.scala 146:33]
  wire  Ns_9_7 = PsReg_7[9]; // @[MulModule.scala 146:33]
  wire  Ns_9_8 = PsReg_8[9]; // @[MulModule.scala 146:33]
  wire  Ns_9_9 = PsReg_9[9]; // @[MulModule.scala 146:33]
  wire  Ns_9_10 = PsReg_10[9]; // @[MulModule.scala 146:33]
  wire  Ns_9_11 = PsReg_11[9]; // @[MulModule.scala 146:33]
  wire  Ns_9_12 = PsReg_12[9]; // @[MulModule.scala 146:33]
  wire  Ns_9_13 = PsReg_13[9]; // @[MulModule.scala 146:33]
  wire  Ns_9_14 = PsReg_14[9]; // @[MulModule.scala 146:33]
  wire  Ns_9_15 = PsReg_15[9]; // @[MulModule.scala 146:33]
  wire  Ns_10_0 = PsReg_0[10]; // @[MulModule.scala 146:33]
  wire  Ns_10_1 = PsReg_1[10]; // @[MulModule.scala 146:33]
  wire  Ns_10_2 = PsReg_2[10]; // @[MulModule.scala 146:33]
  wire  Ns_10_3 = PsReg_3[10]; // @[MulModule.scala 146:33]
  wire  Ns_10_4 = PsReg_4[10]; // @[MulModule.scala 146:33]
  wire  Ns_10_5 = PsReg_5[10]; // @[MulModule.scala 146:33]
  wire  Ns_10_6 = PsReg_6[10]; // @[MulModule.scala 146:33]
  wire  Ns_10_7 = PsReg_7[10]; // @[MulModule.scala 146:33]
  wire  Ns_10_8 = PsReg_8[10]; // @[MulModule.scala 146:33]
  wire  Ns_10_9 = PsReg_9[10]; // @[MulModule.scala 146:33]
  wire  Ns_10_10 = PsReg_10[10]; // @[MulModule.scala 146:33]
  wire  Ns_10_11 = PsReg_11[10]; // @[MulModule.scala 146:33]
  wire  Ns_10_12 = PsReg_12[10]; // @[MulModule.scala 146:33]
  wire  Ns_10_13 = PsReg_13[10]; // @[MulModule.scala 146:33]
  wire  Ns_10_14 = PsReg_14[10]; // @[MulModule.scala 146:33]
  wire  Ns_10_15 = PsReg_15[10]; // @[MulModule.scala 146:33]
  wire  Ns_11_0 = PsReg_0[11]; // @[MulModule.scala 146:33]
  wire  Ns_11_1 = PsReg_1[11]; // @[MulModule.scala 146:33]
  wire  Ns_11_2 = PsReg_2[11]; // @[MulModule.scala 146:33]
  wire  Ns_11_3 = PsReg_3[11]; // @[MulModule.scala 146:33]
  wire  Ns_11_4 = PsReg_4[11]; // @[MulModule.scala 146:33]
  wire  Ns_11_5 = PsReg_5[11]; // @[MulModule.scala 146:33]
  wire  Ns_11_6 = PsReg_6[11]; // @[MulModule.scala 146:33]
  wire  Ns_11_7 = PsReg_7[11]; // @[MulModule.scala 146:33]
  wire  Ns_11_8 = PsReg_8[11]; // @[MulModule.scala 146:33]
  wire  Ns_11_9 = PsReg_9[11]; // @[MulModule.scala 146:33]
  wire  Ns_11_10 = PsReg_10[11]; // @[MulModule.scala 146:33]
  wire  Ns_11_11 = PsReg_11[11]; // @[MulModule.scala 146:33]
  wire  Ns_11_12 = PsReg_12[11]; // @[MulModule.scala 146:33]
  wire  Ns_11_13 = PsReg_13[11]; // @[MulModule.scala 146:33]
  wire  Ns_11_14 = PsReg_14[11]; // @[MulModule.scala 146:33]
  wire  Ns_11_15 = PsReg_15[11]; // @[MulModule.scala 146:33]
  wire  Ns_12_0 = PsReg_0[12]; // @[MulModule.scala 146:33]
  wire  Ns_12_1 = PsReg_1[12]; // @[MulModule.scala 146:33]
  wire  Ns_12_2 = PsReg_2[12]; // @[MulModule.scala 146:33]
  wire  Ns_12_3 = PsReg_3[12]; // @[MulModule.scala 146:33]
  wire  Ns_12_4 = PsReg_4[12]; // @[MulModule.scala 146:33]
  wire  Ns_12_5 = PsReg_5[12]; // @[MulModule.scala 146:33]
  wire  Ns_12_6 = PsReg_6[12]; // @[MulModule.scala 146:33]
  wire  Ns_12_7 = PsReg_7[12]; // @[MulModule.scala 146:33]
  wire  Ns_12_8 = PsReg_8[12]; // @[MulModule.scala 146:33]
  wire  Ns_12_9 = PsReg_9[12]; // @[MulModule.scala 146:33]
  wire  Ns_12_10 = PsReg_10[12]; // @[MulModule.scala 146:33]
  wire  Ns_12_11 = PsReg_11[12]; // @[MulModule.scala 146:33]
  wire  Ns_12_12 = PsReg_12[12]; // @[MulModule.scala 146:33]
  wire  Ns_12_13 = PsReg_13[12]; // @[MulModule.scala 146:33]
  wire  Ns_12_14 = PsReg_14[12]; // @[MulModule.scala 146:33]
  wire  Ns_12_15 = PsReg_15[12]; // @[MulModule.scala 146:33]
  wire  Ns_13_0 = PsReg_0[13]; // @[MulModule.scala 146:33]
  wire  Ns_13_1 = PsReg_1[13]; // @[MulModule.scala 146:33]
  wire  Ns_13_2 = PsReg_2[13]; // @[MulModule.scala 146:33]
  wire  Ns_13_3 = PsReg_3[13]; // @[MulModule.scala 146:33]
  wire  Ns_13_4 = PsReg_4[13]; // @[MulModule.scala 146:33]
  wire  Ns_13_5 = PsReg_5[13]; // @[MulModule.scala 146:33]
  wire  Ns_13_6 = PsReg_6[13]; // @[MulModule.scala 146:33]
  wire  Ns_13_7 = PsReg_7[13]; // @[MulModule.scala 146:33]
  wire  Ns_13_8 = PsReg_8[13]; // @[MulModule.scala 146:33]
  wire  Ns_13_9 = PsReg_9[13]; // @[MulModule.scala 146:33]
  wire  Ns_13_10 = PsReg_10[13]; // @[MulModule.scala 146:33]
  wire  Ns_13_11 = PsReg_11[13]; // @[MulModule.scala 146:33]
  wire  Ns_13_12 = PsReg_12[13]; // @[MulModule.scala 146:33]
  wire  Ns_13_13 = PsReg_13[13]; // @[MulModule.scala 146:33]
  wire  Ns_13_14 = PsReg_14[13]; // @[MulModule.scala 146:33]
  wire  Ns_13_15 = PsReg_15[13]; // @[MulModule.scala 146:33]
  wire  Ns_14_0 = PsReg_0[14]; // @[MulModule.scala 146:33]
  wire  Ns_14_1 = PsReg_1[14]; // @[MulModule.scala 146:33]
  wire  Ns_14_2 = PsReg_2[14]; // @[MulModule.scala 146:33]
  wire  Ns_14_3 = PsReg_3[14]; // @[MulModule.scala 146:33]
  wire  Ns_14_4 = PsReg_4[14]; // @[MulModule.scala 146:33]
  wire  Ns_14_5 = PsReg_5[14]; // @[MulModule.scala 146:33]
  wire  Ns_14_6 = PsReg_6[14]; // @[MulModule.scala 146:33]
  wire  Ns_14_7 = PsReg_7[14]; // @[MulModule.scala 146:33]
  wire  Ns_14_8 = PsReg_8[14]; // @[MulModule.scala 146:33]
  wire  Ns_14_9 = PsReg_9[14]; // @[MulModule.scala 146:33]
  wire  Ns_14_10 = PsReg_10[14]; // @[MulModule.scala 146:33]
  wire  Ns_14_11 = PsReg_11[14]; // @[MulModule.scala 146:33]
  wire  Ns_14_12 = PsReg_12[14]; // @[MulModule.scala 146:33]
  wire  Ns_14_13 = PsReg_13[14]; // @[MulModule.scala 146:33]
  wire  Ns_14_14 = PsReg_14[14]; // @[MulModule.scala 146:33]
  wire  Ns_14_15 = PsReg_15[14]; // @[MulModule.scala 146:33]
  wire  Ns_15_0 = PsReg_0[15]; // @[MulModule.scala 146:33]
  wire  Ns_15_1 = PsReg_1[15]; // @[MulModule.scala 146:33]
  wire  Ns_15_2 = PsReg_2[15]; // @[MulModule.scala 146:33]
  wire  Ns_15_3 = PsReg_3[15]; // @[MulModule.scala 146:33]
  wire  Ns_15_4 = PsReg_4[15]; // @[MulModule.scala 146:33]
  wire  Ns_15_5 = PsReg_5[15]; // @[MulModule.scala 146:33]
  wire  Ns_15_6 = PsReg_6[15]; // @[MulModule.scala 146:33]
  wire  Ns_15_7 = PsReg_7[15]; // @[MulModule.scala 146:33]
  wire  Ns_15_8 = PsReg_8[15]; // @[MulModule.scala 146:33]
  wire  Ns_15_9 = PsReg_9[15]; // @[MulModule.scala 146:33]
  wire  Ns_15_10 = PsReg_10[15]; // @[MulModule.scala 146:33]
  wire  Ns_15_11 = PsReg_11[15]; // @[MulModule.scala 146:33]
  wire  Ns_15_12 = PsReg_12[15]; // @[MulModule.scala 146:33]
  wire  Ns_15_13 = PsReg_13[15]; // @[MulModule.scala 146:33]
  wire  Ns_15_14 = PsReg_14[15]; // @[MulModule.scala 146:33]
  wire  Ns_15_15 = PsReg_15[15]; // @[MulModule.scala 146:33]
  wire  Ns_16_0 = PsReg_0[16]; // @[MulModule.scala 146:33]
  wire  Ns_16_1 = PsReg_1[16]; // @[MulModule.scala 146:33]
  wire  Ns_16_2 = PsReg_2[16]; // @[MulModule.scala 146:33]
  wire  Ns_16_3 = PsReg_3[16]; // @[MulModule.scala 146:33]
  wire  Ns_16_4 = PsReg_4[16]; // @[MulModule.scala 146:33]
  wire  Ns_16_5 = PsReg_5[16]; // @[MulModule.scala 146:33]
  wire  Ns_16_6 = PsReg_6[16]; // @[MulModule.scala 146:33]
  wire  Ns_16_7 = PsReg_7[16]; // @[MulModule.scala 146:33]
  wire  Ns_16_8 = PsReg_8[16]; // @[MulModule.scala 146:33]
  wire  Ns_16_9 = PsReg_9[16]; // @[MulModule.scala 146:33]
  wire  Ns_16_10 = PsReg_10[16]; // @[MulModule.scala 146:33]
  wire  Ns_16_11 = PsReg_11[16]; // @[MulModule.scala 146:33]
  wire  Ns_16_12 = PsReg_12[16]; // @[MulModule.scala 146:33]
  wire  Ns_16_13 = PsReg_13[16]; // @[MulModule.scala 146:33]
  wire  Ns_16_14 = PsReg_14[16]; // @[MulModule.scala 146:33]
  wire  Ns_16_15 = PsReg_15[16]; // @[MulModule.scala 146:33]
  wire  Ns_17_0 = PsReg_0[17]; // @[MulModule.scala 146:33]
  wire  Ns_17_1 = PsReg_1[17]; // @[MulModule.scala 146:33]
  wire  Ns_17_2 = PsReg_2[17]; // @[MulModule.scala 146:33]
  wire  Ns_17_3 = PsReg_3[17]; // @[MulModule.scala 146:33]
  wire  Ns_17_4 = PsReg_4[17]; // @[MulModule.scala 146:33]
  wire  Ns_17_5 = PsReg_5[17]; // @[MulModule.scala 146:33]
  wire  Ns_17_6 = PsReg_6[17]; // @[MulModule.scala 146:33]
  wire  Ns_17_7 = PsReg_7[17]; // @[MulModule.scala 146:33]
  wire  Ns_17_8 = PsReg_8[17]; // @[MulModule.scala 146:33]
  wire  Ns_17_9 = PsReg_9[17]; // @[MulModule.scala 146:33]
  wire  Ns_17_10 = PsReg_10[17]; // @[MulModule.scala 146:33]
  wire  Ns_17_11 = PsReg_11[17]; // @[MulModule.scala 146:33]
  wire  Ns_17_12 = PsReg_12[17]; // @[MulModule.scala 146:33]
  wire  Ns_17_13 = PsReg_13[17]; // @[MulModule.scala 146:33]
  wire  Ns_17_14 = PsReg_14[17]; // @[MulModule.scala 146:33]
  wire  Ns_17_15 = PsReg_15[17]; // @[MulModule.scala 146:33]
  wire  Ns_18_0 = PsReg_0[18]; // @[MulModule.scala 146:33]
  wire  Ns_18_1 = PsReg_1[18]; // @[MulModule.scala 146:33]
  wire  Ns_18_2 = PsReg_2[18]; // @[MulModule.scala 146:33]
  wire  Ns_18_3 = PsReg_3[18]; // @[MulModule.scala 146:33]
  wire  Ns_18_4 = PsReg_4[18]; // @[MulModule.scala 146:33]
  wire  Ns_18_5 = PsReg_5[18]; // @[MulModule.scala 146:33]
  wire  Ns_18_6 = PsReg_6[18]; // @[MulModule.scala 146:33]
  wire  Ns_18_7 = PsReg_7[18]; // @[MulModule.scala 146:33]
  wire  Ns_18_8 = PsReg_8[18]; // @[MulModule.scala 146:33]
  wire  Ns_18_9 = PsReg_9[18]; // @[MulModule.scala 146:33]
  wire  Ns_18_10 = PsReg_10[18]; // @[MulModule.scala 146:33]
  wire  Ns_18_11 = PsReg_11[18]; // @[MulModule.scala 146:33]
  wire  Ns_18_12 = PsReg_12[18]; // @[MulModule.scala 146:33]
  wire  Ns_18_13 = PsReg_13[18]; // @[MulModule.scala 146:33]
  wire  Ns_18_14 = PsReg_14[18]; // @[MulModule.scala 146:33]
  wire  Ns_18_15 = PsReg_15[18]; // @[MulModule.scala 146:33]
  wire  Ns_19_0 = PsReg_0[19]; // @[MulModule.scala 146:33]
  wire  Ns_19_1 = PsReg_1[19]; // @[MulModule.scala 146:33]
  wire  Ns_19_2 = PsReg_2[19]; // @[MulModule.scala 146:33]
  wire  Ns_19_3 = PsReg_3[19]; // @[MulModule.scala 146:33]
  wire  Ns_19_4 = PsReg_4[19]; // @[MulModule.scala 146:33]
  wire  Ns_19_5 = PsReg_5[19]; // @[MulModule.scala 146:33]
  wire  Ns_19_6 = PsReg_6[19]; // @[MulModule.scala 146:33]
  wire  Ns_19_7 = PsReg_7[19]; // @[MulModule.scala 146:33]
  wire  Ns_19_8 = PsReg_8[19]; // @[MulModule.scala 146:33]
  wire  Ns_19_9 = PsReg_9[19]; // @[MulModule.scala 146:33]
  wire  Ns_19_10 = PsReg_10[19]; // @[MulModule.scala 146:33]
  wire  Ns_19_11 = PsReg_11[19]; // @[MulModule.scala 146:33]
  wire  Ns_19_12 = PsReg_12[19]; // @[MulModule.scala 146:33]
  wire  Ns_19_13 = PsReg_13[19]; // @[MulModule.scala 146:33]
  wire  Ns_19_14 = PsReg_14[19]; // @[MulModule.scala 146:33]
  wire  Ns_19_15 = PsReg_15[19]; // @[MulModule.scala 146:33]
  wire  Ns_20_0 = PsReg_0[20]; // @[MulModule.scala 146:33]
  wire  Ns_20_1 = PsReg_1[20]; // @[MulModule.scala 146:33]
  wire  Ns_20_2 = PsReg_2[20]; // @[MulModule.scala 146:33]
  wire  Ns_20_3 = PsReg_3[20]; // @[MulModule.scala 146:33]
  wire  Ns_20_4 = PsReg_4[20]; // @[MulModule.scala 146:33]
  wire  Ns_20_5 = PsReg_5[20]; // @[MulModule.scala 146:33]
  wire  Ns_20_6 = PsReg_6[20]; // @[MulModule.scala 146:33]
  wire  Ns_20_7 = PsReg_7[20]; // @[MulModule.scala 146:33]
  wire  Ns_20_8 = PsReg_8[20]; // @[MulModule.scala 146:33]
  wire  Ns_20_9 = PsReg_9[20]; // @[MulModule.scala 146:33]
  wire  Ns_20_10 = PsReg_10[20]; // @[MulModule.scala 146:33]
  wire  Ns_20_11 = PsReg_11[20]; // @[MulModule.scala 146:33]
  wire  Ns_20_12 = PsReg_12[20]; // @[MulModule.scala 146:33]
  wire  Ns_20_13 = PsReg_13[20]; // @[MulModule.scala 146:33]
  wire  Ns_20_14 = PsReg_14[20]; // @[MulModule.scala 146:33]
  wire  Ns_20_15 = PsReg_15[20]; // @[MulModule.scala 146:33]
  wire  Ns_21_0 = PsReg_0[21]; // @[MulModule.scala 146:33]
  wire  Ns_21_1 = PsReg_1[21]; // @[MulModule.scala 146:33]
  wire  Ns_21_2 = PsReg_2[21]; // @[MulModule.scala 146:33]
  wire  Ns_21_3 = PsReg_3[21]; // @[MulModule.scala 146:33]
  wire  Ns_21_4 = PsReg_4[21]; // @[MulModule.scala 146:33]
  wire  Ns_21_5 = PsReg_5[21]; // @[MulModule.scala 146:33]
  wire  Ns_21_6 = PsReg_6[21]; // @[MulModule.scala 146:33]
  wire  Ns_21_7 = PsReg_7[21]; // @[MulModule.scala 146:33]
  wire  Ns_21_8 = PsReg_8[21]; // @[MulModule.scala 146:33]
  wire  Ns_21_9 = PsReg_9[21]; // @[MulModule.scala 146:33]
  wire  Ns_21_10 = PsReg_10[21]; // @[MulModule.scala 146:33]
  wire  Ns_21_11 = PsReg_11[21]; // @[MulModule.scala 146:33]
  wire  Ns_21_12 = PsReg_12[21]; // @[MulModule.scala 146:33]
  wire  Ns_21_13 = PsReg_13[21]; // @[MulModule.scala 146:33]
  wire  Ns_21_14 = PsReg_14[21]; // @[MulModule.scala 146:33]
  wire  Ns_21_15 = PsReg_15[21]; // @[MulModule.scala 146:33]
  wire  Ns_22_0 = PsReg_0[22]; // @[MulModule.scala 146:33]
  wire  Ns_22_1 = PsReg_1[22]; // @[MulModule.scala 146:33]
  wire  Ns_22_2 = PsReg_2[22]; // @[MulModule.scala 146:33]
  wire  Ns_22_3 = PsReg_3[22]; // @[MulModule.scala 146:33]
  wire  Ns_22_4 = PsReg_4[22]; // @[MulModule.scala 146:33]
  wire  Ns_22_5 = PsReg_5[22]; // @[MulModule.scala 146:33]
  wire  Ns_22_6 = PsReg_6[22]; // @[MulModule.scala 146:33]
  wire  Ns_22_7 = PsReg_7[22]; // @[MulModule.scala 146:33]
  wire  Ns_22_8 = PsReg_8[22]; // @[MulModule.scala 146:33]
  wire  Ns_22_9 = PsReg_9[22]; // @[MulModule.scala 146:33]
  wire  Ns_22_10 = PsReg_10[22]; // @[MulModule.scala 146:33]
  wire  Ns_22_11 = PsReg_11[22]; // @[MulModule.scala 146:33]
  wire  Ns_22_12 = PsReg_12[22]; // @[MulModule.scala 146:33]
  wire  Ns_22_13 = PsReg_13[22]; // @[MulModule.scala 146:33]
  wire  Ns_22_14 = PsReg_14[22]; // @[MulModule.scala 146:33]
  wire  Ns_22_15 = PsReg_15[22]; // @[MulModule.scala 146:33]
  wire  Ns_23_0 = PsReg_0[23]; // @[MulModule.scala 146:33]
  wire  Ns_23_1 = PsReg_1[23]; // @[MulModule.scala 146:33]
  wire  Ns_23_2 = PsReg_2[23]; // @[MulModule.scala 146:33]
  wire  Ns_23_3 = PsReg_3[23]; // @[MulModule.scala 146:33]
  wire  Ns_23_4 = PsReg_4[23]; // @[MulModule.scala 146:33]
  wire  Ns_23_5 = PsReg_5[23]; // @[MulModule.scala 146:33]
  wire  Ns_23_6 = PsReg_6[23]; // @[MulModule.scala 146:33]
  wire  Ns_23_7 = PsReg_7[23]; // @[MulModule.scala 146:33]
  wire  Ns_23_8 = PsReg_8[23]; // @[MulModule.scala 146:33]
  wire  Ns_23_9 = PsReg_9[23]; // @[MulModule.scala 146:33]
  wire  Ns_23_10 = PsReg_10[23]; // @[MulModule.scala 146:33]
  wire  Ns_23_11 = PsReg_11[23]; // @[MulModule.scala 146:33]
  wire  Ns_23_12 = PsReg_12[23]; // @[MulModule.scala 146:33]
  wire  Ns_23_13 = PsReg_13[23]; // @[MulModule.scala 146:33]
  wire  Ns_23_14 = PsReg_14[23]; // @[MulModule.scala 146:33]
  wire  Ns_23_15 = PsReg_15[23]; // @[MulModule.scala 146:33]
  wire  Ns_24_0 = PsReg_0[24]; // @[MulModule.scala 146:33]
  wire  Ns_24_1 = PsReg_1[24]; // @[MulModule.scala 146:33]
  wire  Ns_24_2 = PsReg_2[24]; // @[MulModule.scala 146:33]
  wire  Ns_24_3 = PsReg_3[24]; // @[MulModule.scala 146:33]
  wire  Ns_24_4 = PsReg_4[24]; // @[MulModule.scala 146:33]
  wire  Ns_24_5 = PsReg_5[24]; // @[MulModule.scala 146:33]
  wire  Ns_24_6 = PsReg_6[24]; // @[MulModule.scala 146:33]
  wire  Ns_24_7 = PsReg_7[24]; // @[MulModule.scala 146:33]
  wire  Ns_24_8 = PsReg_8[24]; // @[MulModule.scala 146:33]
  wire  Ns_24_9 = PsReg_9[24]; // @[MulModule.scala 146:33]
  wire  Ns_24_10 = PsReg_10[24]; // @[MulModule.scala 146:33]
  wire  Ns_24_11 = PsReg_11[24]; // @[MulModule.scala 146:33]
  wire  Ns_24_12 = PsReg_12[24]; // @[MulModule.scala 146:33]
  wire  Ns_24_13 = PsReg_13[24]; // @[MulModule.scala 146:33]
  wire  Ns_24_14 = PsReg_14[24]; // @[MulModule.scala 146:33]
  wire  Ns_24_15 = PsReg_15[24]; // @[MulModule.scala 146:33]
  wire  Ns_25_0 = PsReg_0[25]; // @[MulModule.scala 146:33]
  wire  Ns_25_1 = PsReg_1[25]; // @[MulModule.scala 146:33]
  wire  Ns_25_2 = PsReg_2[25]; // @[MulModule.scala 146:33]
  wire  Ns_25_3 = PsReg_3[25]; // @[MulModule.scala 146:33]
  wire  Ns_25_4 = PsReg_4[25]; // @[MulModule.scala 146:33]
  wire  Ns_25_5 = PsReg_5[25]; // @[MulModule.scala 146:33]
  wire  Ns_25_6 = PsReg_6[25]; // @[MulModule.scala 146:33]
  wire  Ns_25_7 = PsReg_7[25]; // @[MulModule.scala 146:33]
  wire  Ns_25_8 = PsReg_8[25]; // @[MulModule.scala 146:33]
  wire  Ns_25_9 = PsReg_9[25]; // @[MulModule.scala 146:33]
  wire  Ns_25_10 = PsReg_10[25]; // @[MulModule.scala 146:33]
  wire  Ns_25_11 = PsReg_11[25]; // @[MulModule.scala 146:33]
  wire  Ns_25_12 = PsReg_12[25]; // @[MulModule.scala 146:33]
  wire  Ns_25_13 = PsReg_13[25]; // @[MulModule.scala 146:33]
  wire  Ns_25_14 = PsReg_14[25]; // @[MulModule.scala 146:33]
  wire  Ns_25_15 = PsReg_15[25]; // @[MulModule.scala 146:33]
  wire  Ns_26_0 = PsReg_0[26]; // @[MulModule.scala 146:33]
  wire  Ns_26_1 = PsReg_1[26]; // @[MulModule.scala 146:33]
  wire  Ns_26_2 = PsReg_2[26]; // @[MulModule.scala 146:33]
  wire  Ns_26_3 = PsReg_3[26]; // @[MulModule.scala 146:33]
  wire  Ns_26_4 = PsReg_4[26]; // @[MulModule.scala 146:33]
  wire  Ns_26_5 = PsReg_5[26]; // @[MulModule.scala 146:33]
  wire  Ns_26_6 = PsReg_6[26]; // @[MulModule.scala 146:33]
  wire  Ns_26_7 = PsReg_7[26]; // @[MulModule.scala 146:33]
  wire  Ns_26_8 = PsReg_8[26]; // @[MulModule.scala 146:33]
  wire  Ns_26_9 = PsReg_9[26]; // @[MulModule.scala 146:33]
  wire  Ns_26_10 = PsReg_10[26]; // @[MulModule.scala 146:33]
  wire  Ns_26_11 = PsReg_11[26]; // @[MulModule.scala 146:33]
  wire  Ns_26_12 = PsReg_12[26]; // @[MulModule.scala 146:33]
  wire  Ns_26_13 = PsReg_13[26]; // @[MulModule.scala 146:33]
  wire  Ns_26_14 = PsReg_14[26]; // @[MulModule.scala 146:33]
  wire  Ns_26_15 = PsReg_15[26]; // @[MulModule.scala 146:33]
  wire  Ns_27_0 = PsReg_0[27]; // @[MulModule.scala 146:33]
  wire  Ns_27_1 = PsReg_1[27]; // @[MulModule.scala 146:33]
  wire  Ns_27_2 = PsReg_2[27]; // @[MulModule.scala 146:33]
  wire  Ns_27_3 = PsReg_3[27]; // @[MulModule.scala 146:33]
  wire  Ns_27_4 = PsReg_4[27]; // @[MulModule.scala 146:33]
  wire  Ns_27_5 = PsReg_5[27]; // @[MulModule.scala 146:33]
  wire  Ns_27_6 = PsReg_6[27]; // @[MulModule.scala 146:33]
  wire  Ns_27_7 = PsReg_7[27]; // @[MulModule.scala 146:33]
  wire  Ns_27_8 = PsReg_8[27]; // @[MulModule.scala 146:33]
  wire  Ns_27_9 = PsReg_9[27]; // @[MulModule.scala 146:33]
  wire  Ns_27_10 = PsReg_10[27]; // @[MulModule.scala 146:33]
  wire  Ns_27_11 = PsReg_11[27]; // @[MulModule.scala 146:33]
  wire  Ns_27_12 = PsReg_12[27]; // @[MulModule.scala 146:33]
  wire  Ns_27_13 = PsReg_13[27]; // @[MulModule.scala 146:33]
  wire  Ns_27_14 = PsReg_14[27]; // @[MulModule.scala 146:33]
  wire  Ns_27_15 = PsReg_15[27]; // @[MulModule.scala 146:33]
  wire  Ns_28_0 = PsReg_0[28]; // @[MulModule.scala 146:33]
  wire  Ns_28_1 = PsReg_1[28]; // @[MulModule.scala 146:33]
  wire  Ns_28_2 = PsReg_2[28]; // @[MulModule.scala 146:33]
  wire  Ns_28_3 = PsReg_3[28]; // @[MulModule.scala 146:33]
  wire  Ns_28_4 = PsReg_4[28]; // @[MulModule.scala 146:33]
  wire  Ns_28_5 = PsReg_5[28]; // @[MulModule.scala 146:33]
  wire  Ns_28_6 = PsReg_6[28]; // @[MulModule.scala 146:33]
  wire  Ns_28_7 = PsReg_7[28]; // @[MulModule.scala 146:33]
  wire  Ns_28_8 = PsReg_8[28]; // @[MulModule.scala 146:33]
  wire  Ns_28_9 = PsReg_9[28]; // @[MulModule.scala 146:33]
  wire  Ns_28_10 = PsReg_10[28]; // @[MulModule.scala 146:33]
  wire  Ns_28_11 = PsReg_11[28]; // @[MulModule.scala 146:33]
  wire  Ns_28_12 = PsReg_12[28]; // @[MulModule.scala 146:33]
  wire  Ns_28_13 = PsReg_13[28]; // @[MulModule.scala 146:33]
  wire  Ns_28_14 = PsReg_14[28]; // @[MulModule.scala 146:33]
  wire  Ns_28_15 = PsReg_15[28]; // @[MulModule.scala 146:33]
  wire  Ns_29_0 = PsReg_0[29]; // @[MulModule.scala 146:33]
  wire  Ns_29_1 = PsReg_1[29]; // @[MulModule.scala 146:33]
  wire  Ns_29_2 = PsReg_2[29]; // @[MulModule.scala 146:33]
  wire  Ns_29_3 = PsReg_3[29]; // @[MulModule.scala 146:33]
  wire  Ns_29_4 = PsReg_4[29]; // @[MulModule.scala 146:33]
  wire  Ns_29_5 = PsReg_5[29]; // @[MulModule.scala 146:33]
  wire  Ns_29_6 = PsReg_6[29]; // @[MulModule.scala 146:33]
  wire  Ns_29_7 = PsReg_7[29]; // @[MulModule.scala 146:33]
  wire  Ns_29_8 = PsReg_8[29]; // @[MulModule.scala 146:33]
  wire  Ns_29_9 = PsReg_9[29]; // @[MulModule.scala 146:33]
  wire  Ns_29_10 = PsReg_10[29]; // @[MulModule.scala 146:33]
  wire  Ns_29_11 = PsReg_11[29]; // @[MulModule.scala 146:33]
  wire  Ns_29_12 = PsReg_12[29]; // @[MulModule.scala 146:33]
  wire  Ns_29_13 = PsReg_13[29]; // @[MulModule.scala 146:33]
  wire  Ns_29_14 = PsReg_14[29]; // @[MulModule.scala 146:33]
  wire  Ns_29_15 = PsReg_15[29]; // @[MulModule.scala 146:33]
  wire  Ns_30_0 = PsReg_0[30]; // @[MulModule.scala 146:33]
  wire  Ns_30_1 = PsReg_1[30]; // @[MulModule.scala 146:33]
  wire  Ns_30_2 = PsReg_2[30]; // @[MulModule.scala 146:33]
  wire  Ns_30_3 = PsReg_3[30]; // @[MulModule.scala 146:33]
  wire  Ns_30_4 = PsReg_4[30]; // @[MulModule.scala 146:33]
  wire  Ns_30_5 = PsReg_5[30]; // @[MulModule.scala 146:33]
  wire  Ns_30_6 = PsReg_6[30]; // @[MulModule.scala 146:33]
  wire  Ns_30_7 = PsReg_7[30]; // @[MulModule.scala 146:33]
  wire  Ns_30_8 = PsReg_8[30]; // @[MulModule.scala 146:33]
  wire  Ns_30_9 = PsReg_9[30]; // @[MulModule.scala 146:33]
  wire  Ns_30_10 = PsReg_10[30]; // @[MulModule.scala 146:33]
  wire  Ns_30_11 = PsReg_11[30]; // @[MulModule.scala 146:33]
  wire  Ns_30_12 = PsReg_12[30]; // @[MulModule.scala 146:33]
  wire  Ns_30_13 = PsReg_13[30]; // @[MulModule.scala 146:33]
  wire  Ns_30_14 = PsReg_14[30]; // @[MulModule.scala 146:33]
  wire  Ns_30_15 = PsReg_15[30]; // @[MulModule.scala 146:33]
  wire  Ns_31_0 = PsReg_0[31]; // @[MulModule.scala 146:33]
  wire  Ns_31_1 = PsReg_1[31]; // @[MulModule.scala 146:33]
  wire  Ns_31_2 = PsReg_2[31]; // @[MulModule.scala 146:33]
  wire  Ns_31_3 = PsReg_3[31]; // @[MulModule.scala 146:33]
  wire  Ns_31_4 = PsReg_4[31]; // @[MulModule.scala 146:33]
  wire  Ns_31_5 = PsReg_5[31]; // @[MulModule.scala 146:33]
  wire  Ns_31_6 = PsReg_6[31]; // @[MulModule.scala 146:33]
  wire  Ns_31_7 = PsReg_7[31]; // @[MulModule.scala 146:33]
  wire  Ns_31_8 = PsReg_8[31]; // @[MulModule.scala 146:33]
  wire  Ns_31_9 = PsReg_9[31]; // @[MulModule.scala 146:33]
  wire  Ns_31_10 = PsReg_10[31]; // @[MulModule.scala 146:33]
  wire  Ns_31_11 = PsReg_11[31]; // @[MulModule.scala 146:33]
  wire  Ns_31_12 = PsReg_12[31]; // @[MulModule.scala 146:33]
  wire  Ns_31_13 = PsReg_13[31]; // @[MulModule.scala 146:33]
  wire  Ns_31_14 = PsReg_14[31]; // @[MulModule.scala 146:33]
  wire  Ns_31_15 = PsReg_15[31]; // @[MulModule.scala 146:33]
  wire [7:0] wt0_io_N_lo = {Ns_0_7,Ns_0_6,Ns_0_5,Ns_0_4,Ns_0_3,Ns_0_2,Ns_0_1,Ns_0_0}; // @[Cat.scala 30:58]
  wire [7:0] wt0_io_N_hi = {Ns_0_15,Ns_0_14,Ns_0_13,Ns_0_12,Ns_0_11,Ns_0_10,Ns_0_9,Ns_0_8}; // @[Cat.scala 30:58]
  wire [7:0] wt1_io_N_lo = {Ns_1_7,Ns_1_6,Ns_1_5,Ns_1_4,Ns_1_3,Ns_1_2,Ns_1_1,Ns_1_0}; // @[Cat.scala 30:58]
  wire [7:0] wt1_io_N_hi = {Ns_1_15,Ns_1_14,Ns_1_13,Ns_1_12,Ns_1_11,Ns_1_10,Ns_1_9,Ns_1_8}; // @[Cat.scala 30:58]
  wire [7:0] wt2_io_N_lo = {Ns_2_7,Ns_2_6,Ns_2_5,Ns_2_4,Ns_2_3,Ns_2_2,Ns_2_1,Ns_2_0}; // @[Cat.scala 30:58]
  wire [7:0] wt2_io_N_hi = {Ns_2_15,Ns_2_14,Ns_2_13,Ns_2_12,Ns_2_11,Ns_2_10,Ns_2_9,Ns_2_8}; // @[Cat.scala 30:58]
  wire [7:0] wt3_io_N_lo = {Ns_3_7,Ns_3_6,Ns_3_5,Ns_3_4,Ns_3_3,Ns_3_2,Ns_3_1,Ns_3_0}; // @[Cat.scala 30:58]
  wire [7:0] wt3_io_N_hi = {Ns_3_15,Ns_3_14,Ns_3_13,Ns_3_12,Ns_3_11,Ns_3_10,Ns_3_9,Ns_3_8}; // @[Cat.scala 30:58]
  wire [7:0] wt4_io_N_lo = {Ns_4_7,Ns_4_6,Ns_4_5,Ns_4_4,Ns_4_3,Ns_4_2,Ns_4_1,Ns_4_0}; // @[Cat.scala 30:58]
  wire [7:0] wt4_io_N_hi = {Ns_4_15,Ns_4_14,Ns_4_13,Ns_4_12,Ns_4_11,Ns_4_10,Ns_4_9,Ns_4_8}; // @[Cat.scala 30:58]
  wire [7:0] wt5_io_N_lo = {Ns_5_7,Ns_5_6,Ns_5_5,Ns_5_4,Ns_5_3,Ns_5_2,Ns_5_1,Ns_5_0}; // @[Cat.scala 30:58]
  wire [7:0] wt5_io_N_hi = {Ns_5_15,Ns_5_14,Ns_5_13,Ns_5_12,Ns_5_11,Ns_5_10,Ns_5_9,Ns_5_8}; // @[Cat.scala 30:58]
  wire [7:0] wt6_io_N_lo = {Ns_6_7,Ns_6_6,Ns_6_5,Ns_6_4,Ns_6_3,Ns_6_2,Ns_6_1,Ns_6_0}; // @[Cat.scala 30:58]
  wire [7:0] wt6_io_N_hi = {Ns_6_15,Ns_6_14,Ns_6_13,Ns_6_12,Ns_6_11,Ns_6_10,Ns_6_9,Ns_6_8}; // @[Cat.scala 30:58]
  wire [7:0] wt7_io_N_lo = {Ns_7_7,Ns_7_6,Ns_7_5,Ns_7_4,Ns_7_3,Ns_7_2,Ns_7_1,Ns_7_0}; // @[Cat.scala 30:58]
  wire [7:0] wt7_io_N_hi = {Ns_7_15,Ns_7_14,Ns_7_13,Ns_7_12,Ns_7_11,Ns_7_10,Ns_7_9,Ns_7_8}; // @[Cat.scala 30:58]
  wire [7:0] wt8_io_N_lo = {Ns_8_7,Ns_8_6,Ns_8_5,Ns_8_4,Ns_8_3,Ns_8_2,Ns_8_1,Ns_8_0}; // @[Cat.scala 30:58]
  wire [7:0] wt8_io_N_hi = {Ns_8_15,Ns_8_14,Ns_8_13,Ns_8_12,Ns_8_11,Ns_8_10,Ns_8_9,Ns_8_8}; // @[Cat.scala 30:58]
  wire [7:0] wt9_io_N_lo = {Ns_9_7,Ns_9_6,Ns_9_5,Ns_9_4,Ns_9_3,Ns_9_2,Ns_9_1,Ns_9_0}; // @[Cat.scala 30:58]
  wire [7:0] wt9_io_N_hi = {Ns_9_15,Ns_9_14,Ns_9_13,Ns_9_12,Ns_9_11,Ns_9_10,Ns_9_9,Ns_9_8}; // @[Cat.scala 30:58]
  wire [7:0] wt10_io_N_lo = {Ns_10_7,Ns_10_6,Ns_10_5,Ns_10_4,Ns_10_3,Ns_10_2,Ns_10_1,Ns_10_0}; // @[Cat.scala 30:58]
  wire [7:0] wt10_io_N_hi = {Ns_10_15,Ns_10_14,Ns_10_13,Ns_10_12,Ns_10_11,Ns_10_10,Ns_10_9,Ns_10_8}; // @[Cat.scala 30:58]
  wire [7:0] wt11_io_N_lo = {Ns_11_7,Ns_11_6,Ns_11_5,Ns_11_4,Ns_11_3,Ns_11_2,Ns_11_1,Ns_11_0}; // @[Cat.scala 30:58]
  wire [7:0] wt11_io_N_hi = {Ns_11_15,Ns_11_14,Ns_11_13,Ns_11_12,Ns_11_11,Ns_11_10,Ns_11_9,Ns_11_8}; // @[Cat.scala 30:58]
  wire [7:0] wt12_io_N_lo = {Ns_12_7,Ns_12_6,Ns_12_5,Ns_12_4,Ns_12_3,Ns_12_2,Ns_12_1,Ns_12_0}; // @[Cat.scala 30:58]
  wire [7:0] wt12_io_N_hi = {Ns_12_15,Ns_12_14,Ns_12_13,Ns_12_12,Ns_12_11,Ns_12_10,Ns_12_9,Ns_12_8}; // @[Cat.scala 30:58]
  wire [7:0] wt13_io_N_lo = {Ns_13_7,Ns_13_6,Ns_13_5,Ns_13_4,Ns_13_3,Ns_13_2,Ns_13_1,Ns_13_0}; // @[Cat.scala 30:58]
  wire [7:0] wt13_io_N_hi = {Ns_13_15,Ns_13_14,Ns_13_13,Ns_13_12,Ns_13_11,Ns_13_10,Ns_13_9,Ns_13_8}; // @[Cat.scala 30:58]
  wire [7:0] wt14_io_N_lo = {Ns_14_7,Ns_14_6,Ns_14_5,Ns_14_4,Ns_14_3,Ns_14_2,Ns_14_1,Ns_14_0}; // @[Cat.scala 30:58]
  wire [7:0] wt14_io_N_hi = {Ns_14_15,Ns_14_14,Ns_14_13,Ns_14_12,Ns_14_11,Ns_14_10,Ns_14_9,Ns_14_8}; // @[Cat.scala 30:58]
  wire [7:0] wt15_io_N_lo = {Ns_15_7,Ns_15_6,Ns_15_5,Ns_15_4,Ns_15_3,Ns_15_2,Ns_15_1,Ns_15_0}; // @[Cat.scala 30:58]
  wire [7:0] wt15_io_N_hi = {Ns_15_15,Ns_15_14,Ns_15_13,Ns_15_12,Ns_15_11,Ns_15_10,Ns_15_9,Ns_15_8}; // @[Cat.scala 30:58]
  wire [7:0] wt16_io_N_lo = {Ns_16_7,Ns_16_6,Ns_16_5,Ns_16_4,Ns_16_3,Ns_16_2,Ns_16_1,Ns_16_0}; // @[Cat.scala 30:58]
  wire [7:0] wt16_io_N_hi = {Ns_16_15,Ns_16_14,Ns_16_13,Ns_16_12,Ns_16_11,Ns_16_10,Ns_16_9,Ns_16_8}; // @[Cat.scala 30:58]
  wire [7:0] wt17_io_N_lo = {Ns_17_7,Ns_17_6,Ns_17_5,Ns_17_4,Ns_17_3,Ns_17_2,Ns_17_1,Ns_17_0}; // @[Cat.scala 30:58]
  wire [7:0] wt17_io_N_hi = {Ns_17_15,Ns_17_14,Ns_17_13,Ns_17_12,Ns_17_11,Ns_17_10,Ns_17_9,Ns_17_8}; // @[Cat.scala 30:58]
  wire [7:0] wt18_io_N_lo = {Ns_18_7,Ns_18_6,Ns_18_5,Ns_18_4,Ns_18_3,Ns_18_2,Ns_18_1,Ns_18_0}; // @[Cat.scala 30:58]
  wire [7:0] wt18_io_N_hi = {Ns_18_15,Ns_18_14,Ns_18_13,Ns_18_12,Ns_18_11,Ns_18_10,Ns_18_9,Ns_18_8}; // @[Cat.scala 30:58]
  wire [7:0] wt19_io_N_lo = {Ns_19_7,Ns_19_6,Ns_19_5,Ns_19_4,Ns_19_3,Ns_19_2,Ns_19_1,Ns_19_0}; // @[Cat.scala 30:58]
  wire [7:0] wt19_io_N_hi = {Ns_19_15,Ns_19_14,Ns_19_13,Ns_19_12,Ns_19_11,Ns_19_10,Ns_19_9,Ns_19_8}; // @[Cat.scala 30:58]
  wire [7:0] wt20_io_N_lo = {Ns_20_7,Ns_20_6,Ns_20_5,Ns_20_4,Ns_20_3,Ns_20_2,Ns_20_1,Ns_20_0}; // @[Cat.scala 30:58]
  wire [7:0] wt20_io_N_hi = {Ns_20_15,Ns_20_14,Ns_20_13,Ns_20_12,Ns_20_11,Ns_20_10,Ns_20_9,Ns_20_8}; // @[Cat.scala 30:58]
  wire [7:0] wt21_io_N_lo = {Ns_21_7,Ns_21_6,Ns_21_5,Ns_21_4,Ns_21_3,Ns_21_2,Ns_21_1,Ns_21_0}; // @[Cat.scala 30:58]
  wire [7:0] wt21_io_N_hi = {Ns_21_15,Ns_21_14,Ns_21_13,Ns_21_12,Ns_21_11,Ns_21_10,Ns_21_9,Ns_21_8}; // @[Cat.scala 30:58]
  wire [7:0] wt22_io_N_lo = {Ns_22_7,Ns_22_6,Ns_22_5,Ns_22_4,Ns_22_3,Ns_22_2,Ns_22_1,Ns_22_0}; // @[Cat.scala 30:58]
  wire [7:0] wt22_io_N_hi = {Ns_22_15,Ns_22_14,Ns_22_13,Ns_22_12,Ns_22_11,Ns_22_10,Ns_22_9,Ns_22_8}; // @[Cat.scala 30:58]
  wire [7:0] wt23_io_N_lo = {Ns_23_7,Ns_23_6,Ns_23_5,Ns_23_4,Ns_23_3,Ns_23_2,Ns_23_1,Ns_23_0}; // @[Cat.scala 30:58]
  wire [7:0] wt23_io_N_hi = {Ns_23_15,Ns_23_14,Ns_23_13,Ns_23_12,Ns_23_11,Ns_23_10,Ns_23_9,Ns_23_8}; // @[Cat.scala 30:58]
  wire [7:0] wt24_io_N_lo = {Ns_24_7,Ns_24_6,Ns_24_5,Ns_24_4,Ns_24_3,Ns_24_2,Ns_24_1,Ns_24_0}; // @[Cat.scala 30:58]
  wire [7:0] wt24_io_N_hi = {Ns_24_15,Ns_24_14,Ns_24_13,Ns_24_12,Ns_24_11,Ns_24_10,Ns_24_9,Ns_24_8}; // @[Cat.scala 30:58]
  wire [7:0] wt25_io_N_lo = {Ns_25_7,Ns_25_6,Ns_25_5,Ns_25_4,Ns_25_3,Ns_25_2,Ns_25_1,Ns_25_0}; // @[Cat.scala 30:58]
  wire [7:0] wt25_io_N_hi = {Ns_25_15,Ns_25_14,Ns_25_13,Ns_25_12,Ns_25_11,Ns_25_10,Ns_25_9,Ns_25_8}; // @[Cat.scala 30:58]
  wire [7:0] wt26_io_N_lo = {Ns_26_7,Ns_26_6,Ns_26_5,Ns_26_4,Ns_26_3,Ns_26_2,Ns_26_1,Ns_26_0}; // @[Cat.scala 30:58]
  wire [7:0] wt26_io_N_hi = {Ns_26_15,Ns_26_14,Ns_26_13,Ns_26_12,Ns_26_11,Ns_26_10,Ns_26_9,Ns_26_8}; // @[Cat.scala 30:58]
  wire [7:0] wt27_io_N_lo = {Ns_27_7,Ns_27_6,Ns_27_5,Ns_27_4,Ns_27_3,Ns_27_2,Ns_27_1,Ns_27_0}; // @[Cat.scala 30:58]
  wire [7:0] wt27_io_N_hi = {Ns_27_15,Ns_27_14,Ns_27_13,Ns_27_12,Ns_27_11,Ns_27_10,Ns_27_9,Ns_27_8}; // @[Cat.scala 30:58]
  wire [7:0] wt28_io_N_lo = {Ns_28_7,Ns_28_6,Ns_28_5,Ns_28_4,Ns_28_3,Ns_28_2,Ns_28_1,Ns_28_0}; // @[Cat.scala 30:58]
  wire [7:0] wt28_io_N_hi = {Ns_28_15,Ns_28_14,Ns_28_13,Ns_28_12,Ns_28_11,Ns_28_10,Ns_28_9,Ns_28_8}; // @[Cat.scala 30:58]
  wire [7:0] wt29_io_N_lo = {Ns_29_7,Ns_29_6,Ns_29_5,Ns_29_4,Ns_29_3,Ns_29_2,Ns_29_1,Ns_29_0}; // @[Cat.scala 30:58]
  wire [7:0] wt29_io_N_hi = {Ns_29_15,Ns_29_14,Ns_29_13,Ns_29_12,Ns_29_11,Ns_29_10,Ns_29_9,Ns_29_8}; // @[Cat.scala 30:58]
  wire [7:0] wt30_io_N_lo = {Ns_30_7,Ns_30_6,Ns_30_5,Ns_30_4,Ns_30_3,Ns_30_2,Ns_30_1,Ns_30_0}; // @[Cat.scala 30:58]
  wire [7:0] wt30_io_N_hi = {Ns_30_15,Ns_30_14,Ns_30_13,Ns_30_12,Ns_30_11,Ns_30_10,Ns_30_9,Ns_30_8}; // @[Cat.scala 30:58]
  wire [7:0] wt31_io_N_lo = {Ns_31_7,Ns_31_6,Ns_31_5,Ns_31_4,Ns_31_3,Ns_31_2,Ns_31_1,Ns_31_0}; // @[Cat.scala 30:58]
  wire [7:0] wt31_io_N_hi = {Ns_31_15,Ns_31_14,Ns_31_13,Ns_31_12,Ns_31_11,Ns_31_10,Ns_31_9,Ns_31_8}; // @[Cat.scala 30:58]
  wire  A_1 = wt0_io_C; // @[MulModule.scala 229:17 MulModule.scala 232:10]
  wire  A_3 = wt2_io_C; // @[MulModule.scala 229:17 MulModule.scala 234:10]
  wire  A_2 = wt1_io_C; // @[MulModule.scala 229:17 MulModule.scala 233:10]
  wire  A_5 = wt4_io_C; // @[MulModule.scala 229:17 MulModule.scala 236:10]
  wire  A_4 = wt3_io_C; // @[MulModule.scala 229:17 MulModule.scala 235:10]
  wire  A_7 = wt6_io_C; // @[MulModule.scala 229:17 MulModule.scala 238:10]
  wire  A_6 = wt5_io_C; // @[MulModule.scala 229:17 MulModule.scala 237:10]
  wire [7:0] trueA_lo_lo = {A_7,A_6,A_5,A_4,A_3,A_2,A_1,csReg_15}; // @[Cat.scala 30:58]
  wire  A_9 = wt8_io_C; // @[MulModule.scala 229:17 MulModule.scala 240:10]
  wire  A_8 = wt7_io_C; // @[MulModule.scala 229:17 MulModule.scala 239:10]
  wire  A_11 = wt10_io_C; // @[MulModule.scala 229:17 MulModule.scala 242:11]
  wire  A_10 = wt9_io_C; // @[MulModule.scala 229:17 MulModule.scala 241:11]
  wire  A_13 = wt12_io_C; // @[MulModule.scala 229:17 MulModule.scala 244:11]
  wire  A_12 = wt11_io_C; // @[MulModule.scala 229:17 MulModule.scala 243:11]
  wire  A_15 = wt14_io_C; // @[MulModule.scala 229:17 MulModule.scala 246:11]
  wire  A_14 = wt13_io_C; // @[MulModule.scala 229:17 MulModule.scala 245:11]
  wire [15:0] trueA_lo = {A_15,A_14,A_13,A_12,A_11,A_10,A_9,A_8,trueA_lo_lo}; // @[Cat.scala 30:58]
  wire  A_17 = wt16_io_C; // @[MulModule.scala 229:17 MulModule.scala 248:11]
  wire  A_16 = wt15_io_C; // @[MulModule.scala 229:17 MulModule.scala 247:11]
  wire  A_19 = wt18_io_C; // @[MulModule.scala 229:17 MulModule.scala 250:11]
  wire  A_18 = wt17_io_C; // @[MulModule.scala 229:17 MulModule.scala 249:11]
  wire  A_21 = wt20_io_C; // @[MulModule.scala 229:17 MulModule.scala 252:11]
  wire  A_20 = wt19_io_C; // @[MulModule.scala 229:17 MulModule.scala 251:11]
  wire  A_23 = wt22_io_C; // @[MulModule.scala 229:17 MulModule.scala 254:11]
  wire  A_22 = wt21_io_C; // @[MulModule.scala 229:17 MulModule.scala 253:11]
  wire [7:0] trueA_hi_lo = {A_23,A_22,A_21,A_20,A_19,A_18,A_17,A_16}; // @[Cat.scala 30:58]
  wire  A_25 = wt24_io_C; // @[MulModule.scala 229:17 MulModule.scala 256:11]
  wire  A_24 = wt23_io_C; // @[MulModule.scala 229:17 MulModule.scala 255:11]
  wire  A_27 = wt26_io_C; // @[MulModule.scala 229:17 MulModule.scala 258:11]
  wire  A_26 = wt25_io_C; // @[MulModule.scala 229:17 MulModule.scala 257:11]
  wire  A_29 = wt28_io_C; // @[MulModule.scala 229:17 MulModule.scala 260:11]
  wire  A_28 = wt27_io_C; // @[MulModule.scala 229:17 MulModule.scala 259:11]
  wire  A_31 = wt30_io_C; // @[MulModule.scala 229:17 MulModule.scala 262:11]
  wire  A_30 = wt29_io_C; // @[MulModule.scala 229:17 MulModule.scala 261:11]
  wire [31:0] trueA = {A_31,A_30,A_29,A_28,A_27,A_26,A_25,A_24,trueA_hi_lo,trueA_lo}; // @[Cat.scala 30:58]
  wire  B_1 = wt1_io_S; // @[MulModule.scala 230:17 MulModule.scala 265:10]
  wire  B_0 = wt0_io_S; // @[MulModule.scala 230:17 MulModule.scala 264:10]
  wire  B_3 = wt3_io_S; // @[MulModule.scala 230:17 MulModule.scala 267:10]
  wire  B_2 = wt2_io_S; // @[MulModule.scala 230:17 MulModule.scala 266:10]
  wire  B_5 = wt5_io_S; // @[MulModule.scala 230:17 MulModule.scala 269:10]
  wire  B_4 = wt4_io_S; // @[MulModule.scala 230:17 MulModule.scala 268:10]
  wire  B_7 = wt7_io_S; // @[MulModule.scala 230:17 MulModule.scala 271:10]
  wire  B_6 = wt6_io_S; // @[MulModule.scala 230:17 MulModule.scala 270:10]
  wire [7:0] trueB_lo_lo = {B_7,B_6,B_5,B_4,B_3,B_2,B_1,B_0}; // @[Cat.scala 30:58]
  wire  B_9 = wt9_io_S; // @[MulModule.scala 230:17 MulModule.scala 273:10]
  wire  B_8 = wt8_io_S; // @[MulModule.scala 230:17 MulModule.scala 272:10]
  wire  B_11 = wt11_io_S; // @[MulModule.scala 230:17 MulModule.scala 275:11]
  wire  B_10 = wt10_io_S; // @[MulModule.scala 230:17 MulModule.scala 274:11]
  wire  B_13 = wt13_io_S; // @[MulModule.scala 230:17 MulModule.scala 277:11]
  wire  B_12 = wt12_io_S; // @[MulModule.scala 230:17 MulModule.scala 276:11]
  wire  B_15 = wt15_io_S; // @[MulModule.scala 230:17 MulModule.scala 279:11]
  wire  B_14 = wt14_io_S; // @[MulModule.scala 230:17 MulModule.scala 278:11]
  wire [15:0] trueB_lo = {B_15,B_14,B_13,B_12,B_11,B_10,B_9,B_8,trueB_lo_lo}; // @[Cat.scala 30:58]
  wire  B_17 = wt17_io_S; // @[MulModule.scala 230:17 MulModule.scala 281:11]
  wire  B_16 = wt16_io_S; // @[MulModule.scala 230:17 MulModule.scala 280:11]
  wire  B_19 = wt19_io_S; // @[MulModule.scala 230:17 MulModule.scala 283:11]
  wire  B_18 = wt18_io_S; // @[MulModule.scala 230:17 MulModule.scala 282:11]
  wire  B_21 = wt21_io_S; // @[MulModule.scala 230:17 MulModule.scala 285:11]
  wire  B_20 = wt20_io_S; // @[MulModule.scala 230:17 MulModule.scala 284:11]
  wire  B_23 = wt23_io_S; // @[MulModule.scala 230:17 MulModule.scala 287:11]
  wire  B_22 = wt22_io_S; // @[MulModule.scala 230:17 MulModule.scala 286:11]
  wire [7:0] trueB_hi_lo = {B_23,B_22,B_21,B_20,B_19,B_18,B_17,B_16}; // @[Cat.scala 30:58]
  wire  B_25 = wt25_io_S; // @[MulModule.scala 230:17 MulModule.scala 289:11]
  wire  B_24 = wt24_io_S; // @[MulModule.scala 230:17 MulModule.scala 288:11]
  wire  B_27 = wt27_io_S; // @[MulModule.scala 230:17 MulModule.scala 291:11]
  wire  B_26 = wt26_io_S; // @[MulModule.scala 230:17 MulModule.scala 290:11]
  wire  B_29 = wt29_io_S; // @[MulModule.scala 230:17 MulModule.scala 293:11]
  wire  B_28 = wt28_io_S; // @[MulModule.scala 230:17 MulModule.scala 292:11]
  wire  B_31 = wt31_io_S; // @[MulModule.scala 230:17 MulModule.scala 295:11]
  wire  B_30 = wt30_io_S; // @[MulModule.scala 230:17 MulModule.scala 294:11]
  wire [31:0] trueB = {B_31,B_30,B_29,B_28,B_27,B_26,B_25,B_24,trueB_hi_lo,trueB_lo}; // @[Cat.scala 30:58]
  wire [31:0] Ps_0 = bc0_io_P; // @[MulModule.scala 14:18 MulModule.scala 68:11]
  wire [31:0] Ps_1 = bc1_io_P; // @[MulModule.scala 14:18 MulModule.scala 69:11]
  wire [31:0] Ps_2 = bc2_io_P; // @[MulModule.scala 14:18 MulModule.scala 70:11]
  wire [31:0] Ps_3 = bc3_io_P; // @[MulModule.scala 14:18 MulModule.scala 71:11]
  wire [31:0] Ps_4 = bc4_io_P; // @[MulModule.scala 14:18 MulModule.scala 72:11]
  wire [31:0] Ps_5 = bc5_io_P; // @[MulModule.scala 14:18 MulModule.scala 73:11]
  wire [31:0] Ps_6 = bc6_io_P; // @[MulModule.scala 14:18 MulModule.scala 74:11]
  wire [31:0] Ps_7 = bc7_io_P; // @[MulModule.scala 14:18 MulModule.scala 75:11]
  wire [31:0] Ps_8 = bc8_io_P; // @[MulModule.scala 14:18 MulModule.scala 76:11]
  wire [31:0] Ps_9 = bc9_io_P; // @[MulModule.scala 14:18 MulModule.scala 77:11]
  wire [31:0] Ps_10 = bc10_io_P; // @[MulModule.scala 14:18 MulModule.scala 78:12]
  wire [31:0] Ps_11 = bc11_io_P; // @[MulModule.scala 14:18 MulModule.scala 79:12]
  wire [31:0] Ps_12 = bc12_io_P; // @[MulModule.scala 14:18 MulModule.scala 80:12]
  wire [31:0] Ps_13 = bc13_io_P; // @[MulModule.scala 14:18 MulModule.scala 81:12]
  wire [31:0] Ps_14 = bc14_io_P; // @[MulModule.scala 14:18 MulModule.scala 82:12]
  wire [31:0] Ps_15 = bc15_io_P; // @[MulModule.scala 14:18 MulModule.scala 83:12]
  wire  cs_0 = bc0_io_c; // @[MulModule.scala 15:18 MulModule.scala 85:11]
  wire  cs_1 = bc1_io_c; // @[MulModule.scala 15:18 MulModule.scala 86:11]
  wire  cs_2 = bc2_io_c; // @[MulModule.scala 15:18 MulModule.scala 87:11]
  wire  cs_3 = bc3_io_c; // @[MulModule.scala 15:18 MulModule.scala 88:11]
  wire  cs_4 = bc4_io_c; // @[MulModule.scala 15:18 MulModule.scala 89:11]
  wire  cs_5 = bc5_io_c; // @[MulModule.scala 15:18 MulModule.scala 90:11]
  wire  cs_6 = bc6_io_c; // @[MulModule.scala 15:18 MulModule.scala 91:11]
  wire  cs_7 = bc7_io_c; // @[MulModule.scala 15:18 MulModule.scala 92:11]
  wire  cs_8 = bc8_io_c; // @[MulModule.scala 15:18 MulModule.scala 93:11]
  wire  cs_9 = bc9_io_c; // @[MulModule.scala 15:18 MulModule.scala 94:11]
  wire  cs_10 = bc10_io_c; // @[MulModule.scala 15:18 MulModule.scala 95:12]
  wire  cs_11 = bc11_io_c; // @[MulModule.scala 15:18 MulModule.scala 96:12]
  wire  cs_12 = bc12_io_c; // @[MulModule.scala 15:18 MulModule.scala 97:12]
  wire  cs_13 = bc13_io_c; // @[MulModule.scala 15:18 MulModule.scala 98:12]
  wire  cs_14 = bc14_io_c; // @[MulModule.scala 15:18 MulModule.scala 99:12]
  wire  cs_15 = bc15_io_c; // @[MulModule.scala 15:18 MulModule.scala 100:12]
  BoothChooser bc0 ( // @[MulModule.scala 17:21]
    .io_X(bc0_io_X),
    .io_y(bc0_io_y),
    .io_P(bc0_io_P),
    .io_c(bc0_io_c)
  );
  BoothChooser bc1 ( // @[MulModule.scala 18:21]
    .io_X(bc1_io_X),
    .io_y(bc1_io_y),
    .io_P(bc1_io_P),
    .io_c(bc1_io_c)
  );
  BoothChooser bc2 ( // @[MulModule.scala 19:21]
    .io_X(bc2_io_X),
    .io_y(bc2_io_y),
    .io_P(bc2_io_P),
    .io_c(bc2_io_c)
  );
  BoothChooser bc3 ( // @[MulModule.scala 20:21]
    .io_X(bc3_io_X),
    .io_y(bc3_io_y),
    .io_P(bc3_io_P),
    .io_c(bc3_io_c)
  );
  BoothChooser bc4 ( // @[MulModule.scala 21:21]
    .io_X(bc4_io_X),
    .io_y(bc4_io_y),
    .io_P(bc4_io_P),
    .io_c(bc4_io_c)
  );
  BoothChooser bc5 ( // @[MulModule.scala 22:21]
    .io_X(bc5_io_X),
    .io_y(bc5_io_y),
    .io_P(bc5_io_P),
    .io_c(bc5_io_c)
  );
  BoothChooser bc6 ( // @[MulModule.scala 23:21]
    .io_X(bc6_io_X),
    .io_y(bc6_io_y),
    .io_P(bc6_io_P),
    .io_c(bc6_io_c)
  );
  BoothChooser bc7 ( // @[MulModule.scala 24:21]
    .io_X(bc7_io_X),
    .io_y(bc7_io_y),
    .io_P(bc7_io_P),
    .io_c(bc7_io_c)
  );
  BoothChooser bc8 ( // @[MulModule.scala 25:21]
    .io_X(bc8_io_X),
    .io_y(bc8_io_y),
    .io_P(bc8_io_P),
    .io_c(bc8_io_c)
  );
  BoothChooser bc9 ( // @[MulModule.scala 26:21]
    .io_X(bc9_io_X),
    .io_y(bc9_io_y),
    .io_P(bc9_io_P),
    .io_c(bc9_io_c)
  );
  BoothChooser bc10 ( // @[MulModule.scala 27:22]
    .io_X(bc10_io_X),
    .io_y(bc10_io_y),
    .io_P(bc10_io_P),
    .io_c(bc10_io_c)
  );
  BoothChooser bc11 ( // @[MulModule.scala 28:22]
    .io_X(bc11_io_X),
    .io_y(bc11_io_y),
    .io_P(bc11_io_P),
    .io_c(bc11_io_c)
  );
  BoothChooser bc12 ( // @[MulModule.scala 29:22]
    .io_X(bc12_io_X),
    .io_y(bc12_io_y),
    .io_P(bc12_io_P),
    .io_c(bc12_io_c)
  );
  BoothChooser bc13 ( // @[MulModule.scala 30:22]
    .io_X(bc13_io_X),
    .io_y(bc13_io_y),
    .io_P(bc13_io_P),
    .io_c(bc13_io_c)
  );
  BoothChooser bc14 ( // @[MulModule.scala 31:22]
    .io_X(bc14_io_X),
    .io_y(bc14_io_y),
    .io_P(bc14_io_P),
    .io_c(bc14_io_c)
  );
  BoothChooser bc15 ( // @[MulModule.scala 32:22]
    .io_X(bc15_io_X),
    .io_y(bc15_io_y),
    .io_P(bc15_io_P),
    .io_c(bc15_io_c)
  );
  WallaceTree16 wt0 ( // @[MulModule.scala 110:21]
    .io_N(wt0_io_N),
    .io_S(wt0_io_S),
    .io_C(wt0_io_C),
    .io_Cin_0(wt0_io_Cin_0),
    .io_Cin_1(wt0_io_Cin_1),
    .io_Cin_2(wt0_io_Cin_2),
    .io_Cin_3(wt0_io_Cin_3),
    .io_Cin_4(wt0_io_Cin_4),
    .io_Cin_5(wt0_io_Cin_5),
    .io_Cin_6(wt0_io_Cin_6),
    .io_Cin_7(wt0_io_Cin_7),
    .io_Cin_8(wt0_io_Cin_8),
    .io_Cin_9(wt0_io_Cin_9),
    .io_Cin_10(wt0_io_Cin_10),
    .io_Cin_11(wt0_io_Cin_11),
    .io_Cin_12(wt0_io_Cin_12),
    .io_Cin_13(wt0_io_Cin_13),
    .io_Cin_14(wt0_io_Cin_14),
    .io_Cout_0(wt0_io_Cout_0),
    .io_Cout_1(wt0_io_Cout_1),
    .io_Cout_2(wt0_io_Cout_2),
    .io_Cout_3(wt0_io_Cout_3),
    .io_Cout_4(wt0_io_Cout_4),
    .io_Cout_5(wt0_io_Cout_5),
    .io_Cout_6(wt0_io_Cout_6),
    .io_Cout_7(wt0_io_Cout_7),
    .io_Cout_8(wt0_io_Cout_8),
    .io_Cout_9(wt0_io_Cout_9),
    .io_Cout_10(wt0_io_Cout_10),
    .io_Cout_11(wt0_io_Cout_11),
    .io_Cout_12(wt0_io_Cout_12),
    .io_Cout_13(wt0_io_Cout_13),
    .io_Cout_14(wt0_io_Cout_14)
  );
  WallaceTree16 wt1 ( // @[MulModule.scala 111:21]
    .io_N(wt1_io_N),
    .io_S(wt1_io_S),
    .io_C(wt1_io_C),
    .io_Cin_0(wt1_io_Cin_0),
    .io_Cin_1(wt1_io_Cin_1),
    .io_Cin_2(wt1_io_Cin_2),
    .io_Cin_3(wt1_io_Cin_3),
    .io_Cin_4(wt1_io_Cin_4),
    .io_Cin_5(wt1_io_Cin_5),
    .io_Cin_6(wt1_io_Cin_6),
    .io_Cin_7(wt1_io_Cin_7),
    .io_Cin_8(wt1_io_Cin_8),
    .io_Cin_9(wt1_io_Cin_9),
    .io_Cin_10(wt1_io_Cin_10),
    .io_Cin_11(wt1_io_Cin_11),
    .io_Cin_12(wt1_io_Cin_12),
    .io_Cin_13(wt1_io_Cin_13),
    .io_Cin_14(wt1_io_Cin_14),
    .io_Cout_0(wt1_io_Cout_0),
    .io_Cout_1(wt1_io_Cout_1),
    .io_Cout_2(wt1_io_Cout_2),
    .io_Cout_3(wt1_io_Cout_3),
    .io_Cout_4(wt1_io_Cout_4),
    .io_Cout_5(wt1_io_Cout_5),
    .io_Cout_6(wt1_io_Cout_6),
    .io_Cout_7(wt1_io_Cout_7),
    .io_Cout_8(wt1_io_Cout_8),
    .io_Cout_9(wt1_io_Cout_9),
    .io_Cout_10(wt1_io_Cout_10),
    .io_Cout_11(wt1_io_Cout_11),
    .io_Cout_12(wt1_io_Cout_12),
    .io_Cout_13(wt1_io_Cout_13),
    .io_Cout_14(wt1_io_Cout_14)
  );
  WallaceTree16 wt2 ( // @[MulModule.scala 112:21]
    .io_N(wt2_io_N),
    .io_S(wt2_io_S),
    .io_C(wt2_io_C),
    .io_Cin_0(wt2_io_Cin_0),
    .io_Cin_1(wt2_io_Cin_1),
    .io_Cin_2(wt2_io_Cin_2),
    .io_Cin_3(wt2_io_Cin_3),
    .io_Cin_4(wt2_io_Cin_4),
    .io_Cin_5(wt2_io_Cin_5),
    .io_Cin_6(wt2_io_Cin_6),
    .io_Cin_7(wt2_io_Cin_7),
    .io_Cin_8(wt2_io_Cin_8),
    .io_Cin_9(wt2_io_Cin_9),
    .io_Cin_10(wt2_io_Cin_10),
    .io_Cin_11(wt2_io_Cin_11),
    .io_Cin_12(wt2_io_Cin_12),
    .io_Cin_13(wt2_io_Cin_13),
    .io_Cin_14(wt2_io_Cin_14),
    .io_Cout_0(wt2_io_Cout_0),
    .io_Cout_1(wt2_io_Cout_1),
    .io_Cout_2(wt2_io_Cout_2),
    .io_Cout_3(wt2_io_Cout_3),
    .io_Cout_4(wt2_io_Cout_4),
    .io_Cout_5(wt2_io_Cout_5),
    .io_Cout_6(wt2_io_Cout_6),
    .io_Cout_7(wt2_io_Cout_7),
    .io_Cout_8(wt2_io_Cout_8),
    .io_Cout_9(wt2_io_Cout_9),
    .io_Cout_10(wt2_io_Cout_10),
    .io_Cout_11(wt2_io_Cout_11),
    .io_Cout_12(wt2_io_Cout_12),
    .io_Cout_13(wt2_io_Cout_13),
    .io_Cout_14(wt2_io_Cout_14)
  );
  WallaceTree16 wt3 ( // @[MulModule.scala 113:21]
    .io_N(wt3_io_N),
    .io_S(wt3_io_S),
    .io_C(wt3_io_C),
    .io_Cin_0(wt3_io_Cin_0),
    .io_Cin_1(wt3_io_Cin_1),
    .io_Cin_2(wt3_io_Cin_2),
    .io_Cin_3(wt3_io_Cin_3),
    .io_Cin_4(wt3_io_Cin_4),
    .io_Cin_5(wt3_io_Cin_5),
    .io_Cin_6(wt3_io_Cin_6),
    .io_Cin_7(wt3_io_Cin_7),
    .io_Cin_8(wt3_io_Cin_8),
    .io_Cin_9(wt3_io_Cin_9),
    .io_Cin_10(wt3_io_Cin_10),
    .io_Cin_11(wt3_io_Cin_11),
    .io_Cin_12(wt3_io_Cin_12),
    .io_Cin_13(wt3_io_Cin_13),
    .io_Cin_14(wt3_io_Cin_14),
    .io_Cout_0(wt3_io_Cout_0),
    .io_Cout_1(wt3_io_Cout_1),
    .io_Cout_2(wt3_io_Cout_2),
    .io_Cout_3(wt3_io_Cout_3),
    .io_Cout_4(wt3_io_Cout_4),
    .io_Cout_5(wt3_io_Cout_5),
    .io_Cout_6(wt3_io_Cout_6),
    .io_Cout_7(wt3_io_Cout_7),
    .io_Cout_8(wt3_io_Cout_8),
    .io_Cout_9(wt3_io_Cout_9),
    .io_Cout_10(wt3_io_Cout_10),
    .io_Cout_11(wt3_io_Cout_11),
    .io_Cout_12(wt3_io_Cout_12),
    .io_Cout_13(wt3_io_Cout_13),
    .io_Cout_14(wt3_io_Cout_14)
  );
  WallaceTree16 wt4 ( // @[MulModule.scala 114:21]
    .io_N(wt4_io_N),
    .io_S(wt4_io_S),
    .io_C(wt4_io_C),
    .io_Cin_0(wt4_io_Cin_0),
    .io_Cin_1(wt4_io_Cin_1),
    .io_Cin_2(wt4_io_Cin_2),
    .io_Cin_3(wt4_io_Cin_3),
    .io_Cin_4(wt4_io_Cin_4),
    .io_Cin_5(wt4_io_Cin_5),
    .io_Cin_6(wt4_io_Cin_6),
    .io_Cin_7(wt4_io_Cin_7),
    .io_Cin_8(wt4_io_Cin_8),
    .io_Cin_9(wt4_io_Cin_9),
    .io_Cin_10(wt4_io_Cin_10),
    .io_Cin_11(wt4_io_Cin_11),
    .io_Cin_12(wt4_io_Cin_12),
    .io_Cin_13(wt4_io_Cin_13),
    .io_Cin_14(wt4_io_Cin_14),
    .io_Cout_0(wt4_io_Cout_0),
    .io_Cout_1(wt4_io_Cout_1),
    .io_Cout_2(wt4_io_Cout_2),
    .io_Cout_3(wt4_io_Cout_3),
    .io_Cout_4(wt4_io_Cout_4),
    .io_Cout_5(wt4_io_Cout_5),
    .io_Cout_6(wt4_io_Cout_6),
    .io_Cout_7(wt4_io_Cout_7),
    .io_Cout_8(wt4_io_Cout_8),
    .io_Cout_9(wt4_io_Cout_9),
    .io_Cout_10(wt4_io_Cout_10),
    .io_Cout_11(wt4_io_Cout_11),
    .io_Cout_12(wt4_io_Cout_12),
    .io_Cout_13(wt4_io_Cout_13),
    .io_Cout_14(wt4_io_Cout_14)
  );
  WallaceTree16 wt5 ( // @[MulModule.scala 115:21]
    .io_N(wt5_io_N),
    .io_S(wt5_io_S),
    .io_C(wt5_io_C),
    .io_Cin_0(wt5_io_Cin_0),
    .io_Cin_1(wt5_io_Cin_1),
    .io_Cin_2(wt5_io_Cin_2),
    .io_Cin_3(wt5_io_Cin_3),
    .io_Cin_4(wt5_io_Cin_4),
    .io_Cin_5(wt5_io_Cin_5),
    .io_Cin_6(wt5_io_Cin_6),
    .io_Cin_7(wt5_io_Cin_7),
    .io_Cin_8(wt5_io_Cin_8),
    .io_Cin_9(wt5_io_Cin_9),
    .io_Cin_10(wt5_io_Cin_10),
    .io_Cin_11(wt5_io_Cin_11),
    .io_Cin_12(wt5_io_Cin_12),
    .io_Cin_13(wt5_io_Cin_13),
    .io_Cin_14(wt5_io_Cin_14),
    .io_Cout_0(wt5_io_Cout_0),
    .io_Cout_1(wt5_io_Cout_1),
    .io_Cout_2(wt5_io_Cout_2),
    .io_Cout_3(wt5_io_Cout_3),
    .io_Cout_4(wt5_io_Cout_4),
    .io_Cout_5(wt5_io_Cout_5),
    .io_Cout_6(wt5_io_Cout_6),
    .io_Cout_7(wt5_io_Cout_7),
    .io_Cout_8(wt5_io_Cout_8),
    .io_Cout_9(wt5_io_Cout_9),
    .io_Cout_10(wt5_io_Cout_10),
    .io_Cout_11(wt5_io_Cout_11),
    .io_Cout_12(wt5_io_Cout_12),
    .io_Cout_13(wt5_io_Cout_13),
    .io_Cout_14(wt5_io_Cout_14)
  );
  WallaceTree16 wt6 ( // @[MulModule.scala 116:21]
    .io_N(wt6_io_N),
    .io_S(wt6_io_S),
    .io_C(wt6_io_C),
    .io_Cin_0(wt6_io_Cin_0),
    .io_Cin_1(wt6_io_Cin_1),
    .io_Cin_2(wt6_io_Cin_2),
    .io_Cin_3(wt6_io_Cin_3),
    .io_Cin_4(wt6_io_Cin_4),
    .io_Cin_5(wt6_io_Cin_5),
    .io_Cin_6(wt6_io_Cin_6),
    .io_Cin_7(wt6_io_Cin_7),
    .io_Cin_8(wt6_io_Cin_8),
    .io_Cin_9(wt6_io_Cin_9),
    .io_Cin_10(wt6_io_Cin_10),
    .io_Cin_11(wt6_io_Cin_11),
    .io_Cin_12(wt6_io_Cin_12),
    .io_Cin_13(wt6_io_Cin_13),
    .io_Cin_14(wt6_io_Cin_14),
    .io_Cout_0(wt6_io_Cout_0),
    .io_Cout_1(wt6_io_Cout_1),
    .io_Cout_2(wt6_io_Cout_2),
    .io_Cout_3(wt6_io_Cout_3),
    .io_Cout_4(wt6_io_Cout_4),
    .io_Cout_5(wt6_io_Cout_5),
    .io_Cout_6(wt6_io_Cout_6),
    .io_Cout_7(wt6_io_Cout_7),
    .io_Cout_8(wt6_io_Cout_8),
    .io_Cout_9(wt6_io_Cout_9),
    .io_Cout_10(wt6_io_Cout_10),
    .io_Cout_11(wt6_io_Cout_11),
    .io_Cout_12(wt6_io_Cout_12),
    .io_Cout_13(wt6_io_Cout_13),
    .io_Cout_14(wt6_io_Cout_14)
  );
  WallaceTree16 wt7 ( // @[MulModule.scala 117:21]
    .io_N(wt7_io_N),
    .io_S(wt7_io_S),
    .io_C(wt7_io_C),
    .io_Cin_0(wt7_io_Cin_0),
    .io_Cin_1(wt7_io_Cin_1),
    .io_Cin_2(wt7_io_Cin_2),
    .io_Cin_3(wt7_io_Cin_3),
    .io_Cin_4(wt7_io_Cin_4),
    .io_Cin_5(wt7_io_Cin_5),
    .io_Cin_6(wt7_io_Cin_6),
    .io_Cin_7(wt7_io_Cin_7),
    .io_Cin_8(wt7_io_Cin_8),
    .io_Cin_9(wt7_io_Cin_9),
    .io_Cin_10(wt7_io_Cin_10),
    .io_Cin_11(wt7_io_Cin_11),
    .io_Cin_12(wt7_io_Cin_12),
    .io_Cin_13(wt7_io_Cin_13),
    .io_Cin_14(wt7_io_Cin_14),
    .io_Cout_0(wt7_io_Cout_0),
    .io_Cout_1(wt7_io_Cout_1),
    .io_Cout_2(wt7_io_Cout_2),
    .io_Cout_3(wt7_io_Cout_3),
    .io_Cout_4(wt7_io_Cout_4),
    .io_Cout_5(wt7_io_Cout_5),
    .io_Cout_6(wt7_io_Cout_6),
    .io_Cout_7(wt7_io_Cout_7),
    .io_Cout_8(wt7_io_Cout_8),
    .io_Cout_9(wt7_io_Cout_9),
    .io_Cout_10(wt7_io_Cout_10),
    .io_Cout_11(wt7_io_Cout_11),
    .io_Cout_12(wt7_io_Cout_12),
    .io_Cout_13(wt7_io_Cout_13),
    .io_Cout_14(wt7_io_Cout_14)
  );
  WallaceTree16 wt8 ( // @[MulModule.scala 118:21]
    .io_N(wt8_io_N),
    .io_S(wt8_io_S),
    .io_C(wt8_io_C),
    .io_Cin_0(wt8_io_Cin_0),
    .io_Cin_1(wt8_io_Cin_1),
    .io_Cin_2(wt8_io_Cin_2),
    .io_Cin_3(wt8_io_Cin_3),
    .io_Cin_4(wt8_io_Cin_4),
    .io_Cin_5(wt8_io_Cin_5),
    .io_Cin_6(wt8_io_Cin_6),
    .io_Cin_7(wt8_io_Cin_7),
    .io_Cin_8(wt8_io_Cin_8),
    .io_Cin_9(wt8_io_Cin_9),
    .io_Cin_10(wt8_io_Cin_10),
    .io_Cin_11(wt8_io_Cin_11),
    .io_Cin_12(wt8_io_Cin_12),
    .io_Cin_13(wt8_io_Cin_13),
    .io_Cin_14(wt8_io_Cin_14),
    .io_Cout_0(wt8_io_Cout_0),
    .io_Cout_1(wt8_io_Cout_1),
    .io_Cout_2(wt8_io_Cout_2),
    .io_Cout_3(wt8_io_Cout_3),
    .io_Cout_4(wt8_io_Cout_4),
    .io_Cout_5(wt8_io_Cout_5),
    .io_Cout_6(wt8_io_Cout_6),
    .io_Cout_7(wt8_io_Cout_7),
    .io_Cout_8(wt8_io_Cout_8),
    .io_Cout_9(wt8_io_Cout_9),
    .io_Cout_10(wt8_io_Cout_10),
    .io_Cout_11(wt8_io_Cout_11),
    .io_Cout_12(wt8_io_Cout_12),
    .io_Cout_13(wt8_io_Cout_13),
    .io_Cout_14(wt8_io_Cout_14)
  );
  WallaceTree16 wt9 ( // @[MulModule.scala 119:21]
    .io_N(wt9_io_N),
    .io_S(wt9_io_S),
    .io_C(wt9_io_C),
    .io_Cin_0(wt9_io_Cin_0),
    .io_Cin_1(wt9_io_Cin_1),
    .io_Cin_2(wt9_io_Cin_2),
    .io_Cin_3(wt9_io_Cin_3),
    .io_Cin_4(wt9_io_Cin_4),
    .io_Cin_5(wt9_io_Cin_5),
    .io_Cin_6(wt9_io_Cin_6),
    .io_Cin_7(wt9_io_Cin_7),
    .io_Cin_8(wt9_io_Cin_8),
    .io_Cin_9(wt9_io_Cin_9),
    .io_Cin_10(wt9_io_Cin_10),
    .io_Cin_11(wt9_io_Cin_11),
    .io_Cin_12(wt9_io_Cin_12),
    .io_Cin_13(wt9_io_Cin_13),
    .io_Cin_14(wt9_io_Cin_14),
    .io_Cout_0(wt9_io_Cout_0),
    .io_Cout_1(wt9_io_Cout_1),
    .io_Cout_2(wt9_io_Cout_2),
    .io_Cout_3(wt9_io_Cout_3),
    .io_Cout_4(wt9_io_Cout_4),
    .io_Cout_5(wt9_io_Cout_5),
    .io_Cout_6(wt9_io_Cout_6),
    .io_Cout_7(wt9_io_Cout_7),
    .io_Cout_8(wt9_io_Cout_8),
    .io_Cout_9(wt9_io_Cout_9),
    .io_Cout_10(wt9_io_Cout_10),
    .io_Cout_11(wt9_io_Cout_11),
    .io_Cout_12(wt9_io_Cout_12),
    .io_Cout_13(wt9_io_Cout_13),
    .io_Cout_14(wt9_io_Cout_14)
  );
  WallaceTree16 wt10 ( // @[MulModule.scala 120:22]
    .io_N(wt10_io_N),
    .io_S(wt10_io_S),
    .io_C(wt10_io_C),
    .io_Cin_0(wt10_io_Cin_0),
    .io_Cin_1(wt10_io_Cin_1),
    .io_Cin_2(wt10_io_Cin_2),
    .io_Cin_3(wt10_io_Cin_3),
    .io_Cin_4(wt10_io_Cin_4),
    .io_Cin_5(wt10_io_Cin_5),
    .io_Cin_6(wt10_io_Cin_6),
    .io_Cin_7(wt10_io_Cin_7),
    .io_Cin_8(wt10_io_Cin_8),
    .io_Cin_9(wt10_io_Cin_9),
    .io_Cin_10(wt10_io_Cin_10),
    .io_Cin_11(wt10_io_Cin_11),
    .io_Cin_12(wt10_io_Cin_12),
    .io_Cin_13(wt10_io_Cin_13),
    .io_Cin_14(wt10_io_Cin_14),
    .io_Cout_0(wt10_io_Cout_0),
    .io_Cout_1(wt10_io_Cout_1),
    .io_Cout_2(wt10_io_Cout_2),
    .io_Cout_3(wt10_io_Cout_3),
    .io_Cout_4(wt10_io_Cout_4),
    .io_Cout_5(wt10_io_Cout_5),
    .io_Cout_6(wt10_io_Cout_6),
    .io_Cout_7(wt10_io_Cout_7),
    .io_Cout_8(wt10_io_Cout_8),
    .io_Cout_9(wt10_io_Cout_9),
    .io_Cout_10(wt10_io_Cout_10),
    .io_Cout_11(wt10_io_Cout_11),
    .io_Cout_12(wt10_io_Cout_12),
    .io_Cout_13(wt10_io_Cout_13),
    .io_Cout_14(wt10_io_Cout_14)
  );
  WallaceTree16 wt11 ( // @[MulModule.scala 121:22]
    .io_N(wt11_io_N),
    .io_S(wt11_io_S),
    .io_C(wt11_io_C),
    .io_Cin_0(wt11_io_Cin_0),
    .io_Cin_1(wt11_io_Cin_1),
    .io_Cin_2(wt11_io_Cin_2),
    .io_Cin_3(wt11_io_Cin_3),
    .io_Cin_4(wt11_io_Cin_4),
    .io_Cin_5(wt11_io_Cin_5),
    .io_Cin_6(wt11_io_Cin_6),
    .io_Cin_7(wt11_io_Cin_7),
    .io_Cin_8(wt11_io_Cin_8),
    .io_Cin_9(wt11_io_Cin_9),
    .io_Cin_10(wt11_io_Cin_10),
    .io_Cin_11(wt11_io_Cin_11),
    .io_Cin_12(wt11_io_Cin_12),
    .io_Cin_13(wt11_io_Cin_13),
    .io_Cin_14(wt11_io_Cin_14),
    .io_Cout_0(wt11_io_Cout_0),
    .io_Cout_1(wt11_io_Cout_1),
    .io_Cout_2(wt11_io_Cout_2),
    .io_Cout_3(wt11_io_Cout_3),
    .io_Cout_4(wt11_io_Cout_4),
    .io_Cout_5(wt11_io_Cout_5),
    .io_Cout_6(wt11_io_Cout_6),
    .io_Cout_7(wt11_io_Cout_7),
    .io_Cout_8(wt11_io_Cout_8),
    .io_Cout_9(wt11_io_Cout_9),
    .io_Cout_10(wt11_io_Cout_10),
    .io_Cout_11(wt11_io_Cout_11),
    .io_Cout_12(wt11_io_Cout_12),
    .io_Cout_13(wt11_io_Cout_13),
    .io_Cout_14(wt11_io_Cout_14)
  );
  WallaceTree16 wt12 ( // @[MulModule.scala 122:22]
    .io_N(wt12_io_N),
    .io_S(wt12_io_S),
    .io_C(wt12_io_C),
    .io_Cin_0(wt12_io_Cin_0),
    .io_Cin_1(wt12_io_Cin_1),
    .io_Cin_2(wt12_io_Cin_2),
    .io_Cin_3(wt12_io_Cin_3),
    .io_Cin_4(wt12_io_Cin_4),
    .io_Cin_5(wt12_io_Cin_5),
    .io_Cin_6(wt12_io_Cin_6),
    .io_Cin_7(wt12_io_Cin_7),
    .io_Cin_8(wt12_io_Cin_8),
    .io_Cin_9(wt12_io_Cin_9),
    .io_Cin_10(wt12_io_Cin_10),
    .io_Cin_11(wt12_io_Cin_11),
    .io_Cin_12(wt12_io_Cin_12),
    .io_Cin_13(wt12_io_Cin_13),
    .io_Cin_14(wt12_io_Cin_14),
    .io_Cout_0(wt12_io_Cout_0),
    .io_Cout_1(wt12_io_Cout_1),
    .io_Cout_2(wt12_io_Cout_2),
    .io_Cout_3(wt12_io_Cout_3),
    .io_Cout_4(wt12_io_Cout_4),
    .io_Cout_5(wt12_io_Cout_5),
    .io_Cout_6(wt12_io_Cout_6),
    .io_Cout_7(wt12_io_Cout_7),
    .io_Cout_8(wt12_io_Cout_8),
    .io_Cout_9(wt12_io_Cout_9),
    .io_Cout_10(wt12_io_Cout_10),
    .io_Cout_11(wt12_io_Cout_11),
    .io_Cout_12(wt12_io_Cout_12),
    .io_Cout_13(wt12_io_Cout_13),
    .io_Cout_14(wt12_io_Cout_14)
  );
  WallaceTree16 wt13 ( // @[MulModule.scala 123:22]
    .io_N(wt13_io_N),
    .io_S(wt13_io_S),
    .io_C(wt13_io_C),
    .io_Cin_0(wt13_io_Cin_0),
    .io_Cin_1(wt13_io_Cin_1),
    .io_Cin_2(wt13_io_Cin_2),
    .io_Cin_3(wt13_io_Cin_3),
    .io_Cin_4(wt13_io_Cin_4),
    .io_Cin_5(wt13_io_Cin_5),
    .io_Cin_6(wt13_io_Cin_6),
    .io_Cin_7(wt13_io_Cin_7),
    .io_Cin_8(wt13_io_Cin_8),
    .io_Cin_9(wt13_io_Cin_9),
    .io_Cin_10(wt13_io_Cin_10),
    .io_Cin_11(wt13_io_Cin_11),
    .io_Cin_12(wt13_io_Cin_12),
    .io_Cin_13(wt13_io_Cin_13),
    .io_Cin_14(wt13_io_Cin_14),
    .io_Cout_0(wt13_io_Cout_0),
    .io_Cout_1(wt13_io_Cout_1),
    .io_Cout_2(wt13_io_Cout_2),
    .io_Cout_3(wt13_io_Cout_3),
    .io_Cout_4(wt13_io_Cout_4),
    .io_Cout_5(wt13_io_Cout_5),
    .io_Cout_6(wt13_io_Cout_6),
    .io_Cout_7(wt13_io_Cout_7),
    .io_Cout_8(wt13_io_Cout_8),
    .io_Cout_9(wt13_io_Cout_9),
    .io_Cout_10(wt13_io_Cout_10),
    .io_Cout_11(wt13_io_Cout_11),
    .io_Cout_12(wt13_io_Cout_12),
    .io_Cout_13(wt13_io_Cout_13),
    .io_Cout_14(wt13_io_Cout_14)
  );
  WallaceTree16 wt14 ( // @[MulModule.scala 124:22]
    .io_N(wt14_io_N),
    .io_S(wt14_io_S),
    .io_C(wt14_io_C),
    .io_Cin_0(wt14_io_Cin_0),
    .io_Cin_1(wt14_io_Cin_1),
    .io_Cin_2(wt14_io_Cin_2),
    .io_Cin_3(wt14_io_Cin_3),
    .io_Cin_4(wt14_io_Cin_4),
    .io_Cin_5(wt14_io_Cin_5),
    .io_Cin_6(wt14_io_Cin_6),
    .io_Cin_7(wt14_io_Cin_7),
    .io_Cin_8(wt14_io_Cin_8),
    .io_Cin_9(wt14_io_Cin_9),
    .io_Cin_10(wt14_io_Cin_10),
    .io_Cin_11(wt14_io_Cin_11),
    .io_Cin_12(wt14_io_Cin_12),
    .io_Cin_13(wt14_io_Cin_13),
    .io_Cin_14(wt14_io_Cin_14),
    .io_Cout_0(wt14_io_Cout_0),
    .io_Cout_1(wt14_io_Cout_1),
    .io_Cout_2(wt14_io_Cout_2),
    .io_Cout_3(wt14_io_Cout_3),
    .io_Cout_4(wt14_io_Cout_4),
    .io_Cout_5(wt14_io_Cout_5),
    .io_Cout_6(wt14_io_Cout_6),
    .io_Cout_7(wt14_io_Cout_7),
    .io_Cout_8(wt14_io_Cout_8),
    .io_Cout_9(wt14_io_Cout_9),
    .io_Cout_10(wt14_io_Cout_10),
    .io_Cout_11(wt14_io_Cout_11),
    .io_Cout_12(wt14_io_Cout_12),
    .io_Cout_13(wt14_io_Cout_13),
    .io_Cout_14(wt14_io_Cout_14)
  );
  WallaceTree16 wt15 ( // @[MulModule.scala 125:22]
    .io_N(wt15_io_N),
    .io_S(wt15_io_S),
    .io_C(wt15_io_C),
    .io_Cin_0(wt15_io_Cin_0),
    .io_Cin_1(wt15_io_Cin_1),
    .io_Cin_2(wt15_io_Cin_2),
    .io_Cin_3(wt15_io_Cin_3),
    .io_Cin_4(wt15_io_Cin_4),
    .io_Cin_5(wt15_io_Cin_5),
    .io_Cin_6(wt15_io_Cin_6),
    .io_Cin_7(wt15_io_Cin_7),
    .io_Cin_8(wt15_io_Cin_8),
    .io_Cin_9(wt15_io_Cin_9),
    .io_Cin_10(wt15_io_Cin_10),
    .io_Cin_11(wt15_io_Cin_11),
    .io_Cin_12(wt15_io_Cin_12),
    .io_Cin_13(wt15_io_Cin_13),
    .io_Cin_14(wt15_io_Cin_14),
    .io_Cout_0(wt15_io_Cout_0),
    .io_Cout_1(wt15_io_Cout_1),
    .io_Cout_2(wt15_io_Cout_2),
    .io_Cout_3(wt15_io_Cout_3),
    .io_Cout_4(wt15_io_Cout_4),
    .io_Cout_5(wt15_io_Cout_5),
    .io_Cout_6(wt15_io_Cout_6),
    .io_Cout_7(wt15_io_Cout_7),
    .io_Cout_8(wt15_io_Cout_8),
    .io_Cout_9(wt15_io_Cout_9),
    .io_Cout_10(wt15_io_Cout_10),
    .io_Cout_11(wt15_io_Cout_11),
    .io_Cout_12(wt15_io_Cout_12),
    .io_Cout_13(wt15_io_Cout_13),
    .io_Cout_14(wt15_io_Cout_14)
  );
  WallaceTree16 wt16 ( // @[MulModule.scala 126:22]
    .io_N(wt16_io_N),
    .io_S(wt16_io_S),
    .io_C(wt16_io_C),
    .io_Cin_0(wt16_io_Cin_0),
    .io_Cin_1(wt16_io_Cin_1),
    .io_Cin_2(wt16_io_Cin_2),
    .io_Cin_3(wt16_io_Cin_3),
    .io_Cin_4(wt16_io_Cin_4),
    .io_Cin_5(wt16_io_Cin_5),
    .io_Cin_6(wt16_io_Cin_6),
    .io_Cin_7(wt16_io_Cin_7),
    .io_Cin_8(wt16_io_Cin_8),
    .io_Cin_9(wt16_io_Cin_9),
    .io_Cin_10(wt16_io_Cin_10),
    .io_Cin_11(wt16_io_Cin_11),
    .io_Cin_12(wt16_io_Cin_12),
    .io_Cin_13(wt16_io_Cin_13),
    .io_Cin_14(wt16_io_Cin_14),
    .io_Cout_0(wt16_io_Cout_0),
    .io_Cout_1(wt16_io_Cout_1),
    .io_Cout_2(wt16_io_Cout_2),
    .io_Cout_3(wt16_io_Cout_3),
    .io_Cout_4(wt16_io_Cout_4),
    .io_Cout_5(wt16_io_Cout_5),
    .io_Cout_6(wt16_io_Cout_6),
    .io_Cout_7(wt16_io_Cout_7),
    .io_Cout_8(wt16_io_Cout_8),
    .io_Cout_9(wt16_io_Cout_9),
    .io_Cout_10(wt16_io_Cout_10),
    .io_Cout_11(wt16_io_Cout_11),
    .io_Cout_12(wt16_io_Cout_12),
    .io_Cout_13(wt16_io_Cout_13),
    .io_Cout_14(wt16_io_Cout_14)
  );
  WallaceTree16 wt17 ( // @[MulModule.scala 127:22]
    .io_N(wt17_io_N),
    .io_S(wt17_io_S),
    .io_C(wt17_io_C),
    .io_Cin_0(wt17_io_Cin_0),
    .io_Cin_1(wt17_io_Cin_1),
    .io_Cin_2(wt17_io_Cin_2),
    .io_Cin_3(wt17_io_Cin_3),
    .io_Cin_4(wt17_io_Cin_4),
    .io_Cin_5(wt17_io_Cin_5),
    .io_Cin_6(wt17_io_Cin_6),
    .io_Cin_7(wt17_io_Cin_7),
    .io_Cin_8(wt17_io_Cin_8),
    .io_Cin_9(wt17_io_Cin_9),
    .io_Cin_10(wt17_io_Cin_10),
    .io_Cin_11(wt17_io_Cin_11),
    .io_Cin_12(wt17_io_Cin_12),
    .io_Cin_13(wt17_io_Cin_13),
    .io_Cin_14(wt17_io_Cin_14),
    .io_Cout_0(wt17_io_Cout_0),
    .io_Cout_1(wt17_io_Cout_1),
    .io_Cout_2(wt17_io_Cout_2),
    .io_Cout_3(wt17_io_Cout_3),
    .io_Cout_4(wt17_io_Cout_4),
    .io_Cout_5(wt17_io_Cout_5),
    .io_Cout_6(wt17_io_Cout_6),
    .io_Cout_7(wt17_io_Cout_7),
    .io_Cout_8(wt17_io_Cout_8),
    .io_Cout_9(wt17_io_Cout_9),
    .io_Cout_10(wt17_io_Cout_10),
    .io_Cout_11(wt17_io_Cout_11),
    .io_Cout_12(wt17_io_Cout_12),
    .io_Cout_13(wt17_io_Cout_13),
    .io_Cout_14(wt17_io_Cout_14)
  );
  WallaceTree16 wt18 ( // @[MulModule.scala 128:22]
    .io_N(wt18_io_N),
    .io_S(wt18_io_S),
    .io_C(wt18_io_C),
    .io_Cin_0(wt18_io_Cin_0),
    .io_Cin_1(wt18_io_Cin_1),
    .io_Cin_2(wt18_io_Cin_2),
    .io_Cin_3(wt18_io_Cin_3),
    .io_Cin_4(wt18_io_Cin_4),
    .io_Cin_5(wt18_io_Cin_5),
    .io_Cin_6(wt18_io_Cin_6),
    .io_Cin_7(wt18_io_Cin_7),
    .io_Cin_8(wt18_io_Cin_8),
    .io_Cin_9(wt18_io_Cin_9),
    .io_Cin_10(wt18_io_Cin_10),
    .io_Cin_11(wt18_io_Cin_11),
    .io_Cin_12(wt18_io_Cin_12),
    .io_Cin_13(wt18_io_Cin_13),
    .io_Cin_14(wt18_io_Cin_14),
    .io_Cout_0(wt18_io_Cout_0),
    .io_Cout_1(wt18_io_Cout_1),
    .io_Cout_2(wt18_io_Cout_2),
    .io_Cout_3(wt18_io_Cout_3),
    .io_Cout_4(wt18_io_Cout_4),
    .io_Cout_5(wt18_io_Cout_5),
    .io_Cout_6(wt18_io_Cout_6),
    .io_Cout_7(wt18_io_Cout_7),
    .io_Cout_8(wt18_io_Cout_8),
    .io_Cout_9(wt18_io_Cout_9),
    .io_Cout_10(wt18_io_Cout_10),
    .io_Cout_11(wt18_io_Cout_11),
    .io_Cout_12(wt18_io_Cout_12),
    .io_Cout_13(wt18_io_Cout_13),
    .io_Cout_14(wt18_io_Cout_14)
  );
  WallaceTree16 wt19 ( // @[MulModule.scala 129:22]
    .io_N(wt19_io_N),
    .io_S(wt19_io_S),
    .io_C(wt19_io_C),
    .io_Cin_0(wt19_io_Cin_0),
    .io_Cin_1(wt19_io_Cin_1),
    .io_Cin_2(wt19_io_Cin_2),
    .io_Cin_3(wt19_io_Cin_3),
    .io_Cin_4(wt19_io_Cin_4),
    .io_Cin_5(wt19_io_Cin_5),
    .io_Cin_6(wt19_io_Cin_6),
    .io_Cin_7(wt19_io_Cin_7),
    .io_Cin_8(wt19_io_Cin_8),
    .io_Cin_9(wt19_io_Cin_9),
    .io_Cin_10(wt19_io_Cin_10),
    .io_Cin_11(wt19_io_Cin_11),
    .io_Cin_12(wt19_io_Cin_12),
    .io_Cin_13(wt19_io_Cin_13),
    .io_Cin_14(wt19_io_Cin_14),
    .io_Cout_0(wt19_io_Cout_0),
    .io_Cout_1(wt19_io_Cout_1),
    .io_Cout_2(wt19_io_Cout_2),
    .io_Cout_3(wt19_io_Cout_3),
    .io_Cout_4(wt19_io_Cout_4),
    .io_Cout_5(wt19_io_Cout_5),
    .io_Cout_6(wt19_io_Cout_6),
    .io_Cout_7(wt19_io_Cout_7),
    .io_Cout_8(wt19_io_Cout_8),
    .io_Cout_9(wt19_io_Cout_9),
    .io_Cout_10(wt19_io_Cout_10),
    .io_Cout_11(wt19_io_Cout_11),
    .io_Cout_12(wt19_io_Cout_12),
    .io_Cout_13(wt19_io_Cout_13),
    .io_Cout_14(wt19_io_Cout_14)
  );
  WallaceTree16 wt20 ( // @[MulModule.scala 130:22]
    .io_N(wt20_io_N),
    .io_S(wt20_io_S),
    .io_C(wt20_io_C),
    .io_Cin_0(wt20_io_Cin_0),
    .io_Cin_1(wt20_io_Cin_1),
    .io_Cin_2(wt20_io_Cin_2),
    .io_Cin_3(wt20_io_Cin_3),
    .io_Cin_4(wt20_io_Cin_4),
    .io_Cin_5(wt20_io_Cin_5),
    .io_Cin_6(wt20_io_Cin_6),
    .io_Cin_7(wt20_io_Cin_7),
    .io_Cin_8(wt20_io_Cin_8),
    .io_Cin_9(wt20_io_Cin_9),
    .io_Cin_10(wt20_io_Cin_10),
    .io_Cin_11(wt20_io_Cin_11),
    .io_Cin_12(wt20_io_Cin_12),
    .io_Cin_13(wt20_io_Cin_13),
    .io_Cin_14(wt20_io_Cin_14),
    .io_Cout_0(wt20_io_Cout_0),
    .io_Cout_1(wt20_io_Cout_1),
    .io_Cout_2(wt20_io_Cout_2),
    .io_Cout_3(wt20_io_Cout_3),
    .io_Cout_4(wt20_io_Cout_4),
    .io_Cout_5(wt20_io_Cout_5),
    .io_Cout_6(wt20_io_Cout_6),
    .io_Cout_7(wt20_io_Cout_7),
    .io_Cout_8(wt20_io_Cout_8),
    .io_Cout_9(wt20_io_Cout_9),
    .io_Cout_10(wt20_io_Cout_10),
    .io_Cout_11(wt20_io_Cout_11),
    .io_Cout_12(wt20_io_Cout_12),
    .io_Cout_13(wt20_io_Cout_13),
    .io_Cout_14(wt20_io_Cout_14)
  );
  WallaceTree16 wt21 ( // @[MulModule.scala 131:22]
    .io_N(wt21_io_N),
    .io_S(wt21_io_S),
    .io_C(wt21_io_C),
    .io_Cin_0(wt21_io_Cin_0),
    .io_Cin_1(wt21_io_Cin_1),
    .io_Cin_2(wt21_io_Cin_2),
    .io_Cin_3(wt21_io_Cin_3),
    .io_Cin_4(wt21_io_Cin_4),
    .io_Cin_5(wt21_io_Cin_5),
    .io_Cin_6(wt21_io_Cin_6),
    .io_Cin_7(wt21_io_Cin_7),
    .io_Cin_8(wt21_io_Cin_8),
    .io_Cin_9(wt21_io_Cin_9),
    .io_Cin_10(wt21_io_Cin_10),
    .io_Cin_11(wt21_io_Cin_11),
    .io_Cin_12(wt21_io_Cin_12),
    .io_Cin_13(wt21_io_Cin_13),
    .io_Cin_14(wt21_io_Cin_14),
    .io_Cout_0(wt21_io_Cout_0),
    .io_Cout_1(wt21_io_Cout_1),
    .io_Cout_2(wt21_io_Cout_2),
    .io_Cout_3(wt21_io_Cout_3),
    .io_Cout_4(wt21_io_Cout_4),
    .io_Cout_5(wt21_io_Cout_5),
    .io_Cout_6(wt21_io_Cout_6),
    .io_Cout_7(wt21_io_Cout_7),
    .io_Cout_8(wt21_io_Cout_8),
    .io_Cout_9(wt21_io_Cout_9),
    .io_Cout_10(wt21_io_Cout_10),
    .io_Cout_11(wt21_io_Cout_11),
    .io_Cout_12(wt21_io_Cout_12),
    .io_Cout_13(wt21_io_Cout_13),
    .io_Cout_14(wt21_io_Cout_14)
  );
  WallaceTree16 wt22 ( // @[MulModule.scala 132:22]
    .io_N(wt22_io_N),
    .io_S(wt22_io_S),
    .io_C(wt22_io_C),
    .io_Cin_0(wt22_io_Cin_0),
    .io_Cin_1(wt22_io_Cin_1),
    .io_Cin_2(wt22_io_Cin_2),
    .io_Cin_3(wt22_io_Cin_3),
    .io_Cin_4(wt22_io_Cin_4),
    .io_Cin_5(wt22_io_Cin_5),
    .io_Cin_6(wt22_io_Cin_6),
    .io_Cin_7(wt22_io_Cin_7),
    .io_Cin_8(wt22_io_Cin_8),
    .io_Cin_9(wt22_io_Cin_9),
    .io_Cin_10(wt22_io_Cin_10),
    .io_Cin_11(wt22_io_Cin_11),
    .io_Cin_12(wt22_io_Cin_12),
    .io_Cin_13(wt22_io_Cin_13),
    .io_Cin_14(wt22_io_Cin_14),
    .io_Cout_0(wt22_io_Cout_0),
    .io_Cout_1(wt22_io_Cout_1),
    .io_Cout_2(wt22_io_Cout_2),
    .io_Cout_3(wt22_io_Cout_3),
    .io_Cout_4(wt22_io_Cout_4),
    .io_Cout_5(wt22_io_Cout_5),
    .io_Cout_6(wt22_io_Cout_6),
    .io_Cout_7(wt22_io_Cout_7),
    .io_Cout_8(wt22_io_Cout_8),
    .io_Cout_9(wt22_io_Cout_9),
    .io_Cout_10(wt22_io_Cout_10),
    .io_Cout_11(wt22_io_Cout_11),
    .io_Cout_12(wt22_io_Cout_12),
    .io_Cout_13(wt22_io_Cout_13),
    .io_Cout_14(wt22_io_Cout_14)
  );
  WallaceTree16 wt23 ( // @[MulModule.scala 133:22]
    .io_N(wt23_io_N),
    .io_S(wt23_io_S),
    .io_C(wt23_io_C),
    .io_Cin_0(wt23_io_Cin_0),
    .io_Cin_1(wt23_io_Cin_1),
    .io_Cin_2(wt23_io_Cin_2),
    .io_Cin_3(wt23_io_Cin_3),
    .io_Cin_4(wt23_io_Cin_4),
    .io_Cin_5(wt23_io_Cin_5),
    .io_Cin_6(wt23_io_Cin_6),
    .io_Cin_7(wt23_io_Cin_7),
    .io_Cin_8(wt23_io_Cin_8),
    .io_Cin_9(wt23_io_Cin_9),
    .io_Cin_10(wt23_io_Cin_10),
    .io_Cin_11(wt23_io_Cin_11),
    .io_Cin_12(wt23_io_Cin_12),
    .io_Cin_13(wt23_io_Cin_13),
    .io_Cin_14(wt23_io_Cin_14),
    .io_Cout_0(wt23_io_Cout_0),
    .io_Cout_1(wt23_io_Cout_1),
    .io_Cout_2(wt23_io_Cout_2),
    .io_Cout_3(wt23_io_Cout_3),
    .io_Cout_4(wt23_io_Cout_4),
    .io_Cout_5(wt23_io_Cout_5),
    .io_Cout_6(wt23_io_Cout_6),
    .io_Cout_7(wt23_io_Cout_7),
    .io_Cout_8(wt23_io_Cout_8),
    .io_Cout_9(wt23_io_Cout_9),
    .io_Cout_10(wt23_io_Cout_10),
    .io_Cout_11(wt23_io_Cout_11),
    .io_Cout_12(wt23_io_Cout_12),
    .io_Cout_13(wt23_io_Cout_13),
    .io_Cout_14(wt23_io_Cout_14)
  );
  WallaceTree16 wt24 ( // @[MulModule.scala 134:22]
    .io_N(wt24_io_N),
    .io_S(wt24_io_S),
    .io_C(wt24_io_C),
    .io_Cin_0(wt24_io_Cin_0),
    .io_Cin_1(wt24_io_Cin_1),
    .io_Cin_2(wt24_io_Cin_2),
    .io_Cin_3(wt24_io_Cin_3),
    .io_Cin_4(wt24_io_Cin_4),
    .io_Cin_5(wt24_io_Cin_5),
    .io_Cin_6(wt24_io_Cin_6),
    .io_Cin_7(wt24_io_Cin_7),
    .io_Cin_8(wt24_io_Cin_8),
    .io_Cin_9(wt24_io_Cin_9),
    .io_Cin_10(wt24_io_Cin_10),
    .io_Cin_11(wt24_io_Cin_11),
    .io_Cin_12(wt24_io_Cin_12),
    .io_Cin_13(wt24_io_Cin_13),
    .io_Cin_14(wt24_io_Cin_14),
    .io_Cout_0(wt24_io_Cout_0),
    .io_Cout_1(wt24_io_Cout_1),
    .io_Cout_2(wt24_io_Cout_2),
    .io_Cout_3(wt24_io_Cout_3),
    .io_Cout_4(wt24_io_Cout_4),
    .io_Cout_5(wt24_io_Cout_5),
    .io_Cout_6(wt24_io_Cout_6),
    .io_Cout_7(wt24_io_Cout_7),
    .io_Cout_8(wt24_io_Cout_8),
    .io_Cout_9(wt24_io_Cout_9),
    .io_Cout_10(wt24_io_Cout_10),
    .io_Cout_11(wt24_io_Cout_11),
    .io_Cout_12(wt24_io_Cout_12),
    .io_Cout_13(wt24_io_Cout_13),
    .io_Cout_14(wt24_io_Cout_14)
  );
  WallaceTree16 wt25 ( // @[MulModule.scala 135:22]
    .io_N(wt25_io_N),
    .io_S(wt25_io_S),
    .io_C(wt25_io_C),
    .io_Cin_0(wt25_io_Cin_0),
    .io_Cin_1(wt25_io_Cin_1),
    .io_Cin_2(wt25_io_Cin_2),
    .io_Cin_3(wt25_io_Cin_3),
    .io_Cin_4(wt25_io_Cin_4),
    .io_Cin_5(wt25_io_Cin_5),
    .io_Cin_6(wt25_io_Cin_6),
    .io_Cin_7(wt25_io_Cin_7),
    .io_Cin_8(wt25_io_Cin_8),
    .io_Cin_9(wt25_io_Cin_9),
    .io_Cin_10(wt25_io_Cin_10),
    .io_Cin_11(wt25_io_Cin_11),
    .io_Cin_12(wt25_io_Cin_12),
    .io_Cin_13(wt25_io_Cin_13),
    .io_Cin_14(wt25_io_Cin_14),
    .io_Cout_0(wt25_io_Cout_0),
    .io_Cout_1(wt25_io_Cout_1),
    .io_Cout_2(wt25_io_Cout_2),
    .io_Cout_3(wt25_io_Cout_3),
    .io_Cout_4(wt25_io_Cout_4),
    .io_Cout_5(wt25_io_Cout_5),
    .io_Cout_6(wt25_io_Cout_6),
    .io_Cout_7(wt25_io_Cout_7),
    .io_Cout_8(wt25_io_Cout_8),
    .io_Cout_9(wt25_io_Cout_9),
    .io_Cout_10(wt25_io_Cout_10),
    .io_Cout_11(wt25_io_Cout_11),
    .io_Cout_12(wt25_io_Cout_12),
    .io_Cout_13(wt25_io_Cout_13),
    .io_Cout_14(wt25_io_Cout_14)
  );
  WallaceTree16 wt26 ( // @[MulModule.scala 136:22]
    .io_N(wt26_io_N),
    .io_S(wt26_io_S),
    .io_C(wt26_io_C),
    .io_Cin_0(wt26_io_Cin_0),
    .io_Cin_1(wt26_io_Cin_1),
    .io_Cin_2(wt26_io_Cin_2),
    .io_Cin_3(wt26_io_Cin_3),
    .io_Cin_4(wt26_io_Cin_4),
    .io_Cin_5(wt26_io_Cin_5),
    .io_Cin_6(wt26_io_Cin_6),
    .io_Cin_7(wt26_io_Cin_7),
    .io_Cin_8(wt26_io_Cin_8),
    .io_Cin_9(wt26_io_Cin_9),
    .io_Cin_10(wt26_io_Cin_10),
    .io_Cin_11(wt26_io_Cin_11),
    .io_Cin_12(wt26_io_Cin_12),
    .io_Cin_13(wt26_io_Cin_13),
    .io_Cin_14(wt26_io_Cin_14),
    .io_Cout_0(wt26_io_Cout_0),
    .io_Cout_1(wt26_io_Cout_1),
    .io_Cout_2(wt26_io_Cout_2),
    .io_Cout_3(wt26_io_Cout_3),
    .io_Cout_4(wt26_io_Cout_4),
    .io_Cout_5(wt26_io_Cout_5),
    .io_Cout_6(wt26_io_Cout_6),
    .io_Cout_7(wt26_io_Cout_7),
    .io_Cout_8(wt26_io_Cout_8),
    .io_Cout_9(wt26_io_Cout_9),
    .io_Cout_10(wt26_io_Cout_10),
    .io_Cout_11(wt26_io_Cout_11),
    .io_Cout_12(wt26_io_Cout_12),
    .io_Cout_13(wt26_io_Cout_13),
    .io_Cout_14(wt26_io_Cout_14)
  );
  WallaceTree16 wt27 ( // @[MulModule.scala 137:22]
    .io_N(wt27_io_N),
    .io_S(wt27_io_S),
    .io_C(wt27_io_C),
    .io_Cin_0(wt27_io_Cin_0),
    .io_Cin_1(wt27_io_Cin_1),
    .io_Cin_2(wt27_io_Cin_2),
    .io_Cin_3(wt27_io_Cin_3),
    .io_Cin_4(wt27_io_Cin_4),
    .io_Cin_5(wt27_io_Cin_5),
    .io_Cin_6(wt27_io_Cin_6),
    .io_Cin_7(wt27_io_Cin_7),
    .io_Cin_8(wt27_io_Cin_8),
    .io_Cin_9(wt27_io_Cin_9),
    .io_Cin_10(wt27_io_Cin_10),
    .io_Cin_11(wt27_io_Cin_11),
    .io_Cin_12(wt27_io_Cin_12),
    .io_Cin_13(wt27_io_Cin_13),
    .io_Cin_14(wt27_io_Cin_14),
    .io_Cout_0(wt27_io_Cout_0),
    .io_Cout_1(wt27_io_Cout_1),
    .io_Cout_2(wt27_io_Cout_2),
    .io_Cout_3(wt27_io_Cout_3),
    .io_Cout_4(wt27_io_Cout_4),
    .io_Cout_5(wt27_io_Cout_5),
    .io_Cout_6(wt27_io_Cout_6),
    .io_Cout_7(wt27_io_Cout_7),
    .io_Cout_8(wt27_io_Cout_8),
    .io_Cout_9(wt27_io_Cout_9),
    .io_Cout_10(wt27_io_Cout_10),
    .io_Cout_11(wt27_io_Cout_11),
    .io_Cout_12(wt27_io_Cout_12),
    .io_Cout_13(wt27_io_Cout_13),
    .io_Cout_14(wt27_io_Cout_14)
  );
  WallaceTree16 wt28 ( // @[MulModule.scala 138:22]
    .io_N(wt28_io_N),
    .io_S(wt28_io_S),
    .io_C(wt28_io_C),
    .io_Cin_0(wt28_io_Cin_0),
    .io_Cin_1(wt28_io_Cin_1),
    .io_Cin_2(wt28_io_Cin_2),
    .io_Cin_3(wt28_io_Cin_3),
    .io_Cin_4(wt28_io_Cin_4),
    .io_Cin_5(wt28_io_Cin_5),
    .io_Cin_6(wt28_io_Cin_6),
    .io_Cin_7(wt28_io_Cin_7),
    .io_Cin_8(wt28_io_Cin_8),
    .io_Cin_9(wt28_io_Cin_9),
    .io_Cin_10(wt28_io_Cin_10),
    .io_Cin_11(wt28_io_Cin_11),
    .io_Cin_12(wt28_io_Cin_12),
    .io_Cin_13(wt28_io_Cin_13),
    .io_Cin_14(wt28_io_Cin_14),
    .io_Cout_0(wt28_io_Cout_0),
    .io_Cout_1(wt28_io_Cout_1),
    .io_Cout_2(wt28_io_Cout_2),
    .io_Cout_3(wt28_io_Cout_3),
    .io_Cout_4(wt28_io_Cout_4),
    .io_Cout_5(wt28_io_Cout_5),
    .io_Cout_6(wt28_io_Cout_6),
    .io_Cout_7(wt28_io_Cout_7),
    .io_Cout_8(wt28_io_Cout_8),
    .io_Cout_9(wt28_io_Cout_9),
    .io_Cout_10(wt28_io_Cout_10),
    .io_Cout_11(wt28_io_Cout_11),
    .io_Cout_12(wt28_io_Cout_12),
    .io_Cout_13(wt28_io_Cout_13),
    .io_Cout_14(wt28_io_Cout_14)
  );
  WallaceTree16 wt29 ( // @[MulModule.scala 139:22]
    .io_N(wt29_io_N),
    .io_S(wt29_io_S),
    .io_C(wt29_io_C),
    .io_Cin_0(wt29_io_Cin_0),
    .io_Cin_1(wt29_io_Cin_1),
    .io_Cin_2(wt29_io_Cin_2),
    .io_Cin_3(wt29_io_Cin_3),
    .io_Cin_4(wt29_io_Cin_4),
    .io_Cin_5(wt29_io_Cin_5),
    .io_Cin_6(wt29_io_Cin_6),
    .io_Cin_7(wt29_io_Cin_7),
    .io_Cin_8(wt29_io_Cin_8),
    .io_Cin_9(wt29_io_Cin_9),
    .io_Cin_10(wt29_io_Cin_10),
    .io_Cin_11(wt29_io_Cin_11),
    .io_Cin_12(wt29_io_Cin_12),
    .io_Cin_13(wt29_io_Cin_13),
    .io_Cin_14(wt29_io_Cin_14),
    .io_Cout_0(wt29_io_Cout_0),
    .io_Cout_1(wt29_io_Cout_1),
    .io_Cout_2(wt29_io_Cout_2),
    .io_Cout_3(wt29_io_Cout_3),
    .io_Cout_4(wt29_io_Cout_4),
    .io_Cout_5(wt29_io_Cout_5),
    .io_Cout_6(wt29_io_Cout_6),
    .io_Cout_7(wt29_io_Cout_7),
    .io_Cout_8(wt29_io_Cout_8),
    .io_Cout_9(wt29_io_Cout_9),
    .io_Cout_10(wt29_io_Cout_10),
    .io_Cout_11(wt29_io_Cout_11),
    .io_Cout_12(wt29_io_Cout_12),
    .io_Cout_13(wt29_io_Cout_13),
    .io_Cout_14(wt29_io_Cout_14)
  );
  WallaceTree16 wt30 ( // @[MulModule.scala 140:22]
    .io_N(wt30_io_N),
    .io_S(wt30_io_S),
    .io_C(wt30_io_C),
    .io_Cin_0(wt30_io_Cin_0),
    .io_Cin_1(wt30_io_Cin_1),
    .io_Cin_2(wt30_io_Cin_2),
    .io_Cin_3(wt30_io_Cin_3),
    .io_Cin_4(wt30_io_Cin_4),
    .io_Cin_5(wt30_io_Cin_5),
    .io_Cin_6(wt30_io_Cin_6),
    .io_Cin_7(wt30_io_Cin_7),
    .io_Cin_8(wt30_io_Cin_8),
    .io_Cin_9(wt30_io_Cin_9),
    .io_Cin_10(wt30_io_Cin_10),
    .io_Cin_11(wt30_io_Cin_11),
    .io_Cin_12(wt30_io_Cin_12),
    .io_Cin_13(wt30_io_Cin_13),
    .io_Cin_14(wt30_io_Cin_14),
    .io_Cout_0(wt30_io_Cout_0),
    .io_Cout_1(wt30_io_Cout_1),
    .io_Cout_2(wt30_io_Cout_2),
    .io_Cout_3(wt30_io_Cout_3),
    .io_Cout_4(wt30_io_Cout_4),
    .io_Cout_5(wt30_io_Cout_5),
    .io_Cout_6(wt30_io_Cout_6),
    .io_Cout_7(wt30_io_Cout_7),
    .io_Cout_8(wt30_io_Cout_8),
    .io_Cout_9(wt30_io_Cout_9),
    .io_Cout_10(wt30_io_Cout_10),
    .io_Cout_11(wt30_io_Cout_11),
    .io_Cout_12(wt30_io_Cout_12),
    .io_Cout_13(wt30_io_Cout_13),
    .io_Cout_14(wt30_io_Cout_14)
  );
  WallaceTree16 wt31 ( // @[MulModule.scala 141:22]
    .io_N(wt31_io_N),
    .io_S(wt31_io_S),
    .io_C(wt31_io_C),
    .io_Cin_0(wt31_io_Cin_0),
    .io_Cin_1(wt31_io_Cin_1),
    .io_Cin_2(wt31_io_Cin_2),
    .io_Cin_3(wt31_io_Cin_3),
    .io_Cin_4(wt31_io_Cin_4),
    .io_Cin_5(wt31_io_Cin_5),
    .io_Cin_6(wt31_io_Cin_6),
    .io_Cin_7(wt31_io_Cin_7),
    .io_Cin_8(wt31_io_Cin_8),
    .io_Cin_9(wt31_io_Cin_9),
    .io_Cin_10(wt31_io_Cin_10),
    .io_Cin_11(wt31_io_Cin_11),
    .io_Cin_12(wt31_io_Cin_12),
    .io_Cin_13(wt31_io_Cin_13),
    .io_Cin_14(wt31_io_Cin_14),
    .io_Cout_0(wt31_io_Cout_0),
    .io_Cout_1(wt31_io_Cout_1),
    .io_Cout_2(wt31_io_Cout_2),
    .io_Cout_3(wt31_io_Cout_3),
    .io_Cout_4(wt31_io_Cout_4),
    .io_Cout_5(wt31_io_Cout_5),
    .io_Cout_6(wt31_io_Cout_6),
    .io_Cout_7(wt31_io_Cout_7),
    .io_Cout_8(wt31_io_Cout_8),
    .io_Cout_9(wt31_io_Cout_9),
    .io_Cout_10(wt31_io_Cout_10),
    .io_Cout_11(wt31_io_Cout_11),
    .io_Cout_12(wt31_io_Cout_12),
    .io_Cout_13(wt31_io_Cout_13),
    .io_Cout_14(wt31_io_Cout_14)
  );
  assign io_ans = trueA + trueB; // @[MulModule.scala 300:21]
  assign bc0_io_X = io_OpA; // @[MulModule.scala 34:14]
  assign bc0_io_y = {bc0_io_y_hi,1'h0}; // @[Cat.scala 30:58]
  assign bc1_io_X = _bc1_io_X_T[31:0]; // @[MulModule.scala 36:30]
  assign bc1_io_y = io_OpB[3:1]; // @[MulModule.scala 37:23]
  assign bc2_io_X = _bc2_io_X_T[31:0]; // @[MulModule.scala 38:30]
  assign bc2_io_y = io_OpB[5:3]; // @[MulModule.scala 39:23]
  assign bc3_io_X = _bc3_io_X_T[31:0]; // @[MulModule.scala 40:30]
  assign bc3_io_y = io_OpB[7:5]; // @[MulModule.scala 41:23]
  assign bc4_io_X = _bc4_io_X_T[31:0]; // @[MulModule.scala 42:30]
  assign bc4_io_y = io_OpB[9:7]; // @[MulModule.scala 43:23]
  assign bc5_io_X = _bc5_io_X_T[31:0]; // @[MulModule.scala 44:31]
  assign bc5_io_y = io_OpB[11:9]; // @[MulModule.scala 45:23]
  assign bc6_io_X = _bc6_io_X_T[31:0]; // @[MulModule.scala 46:31]
  assign bc6_io_y = io_OpB[13:11]; // @[MulModule.scala 47:23]
  assign bc7_io_X = _bc7_io_X_T[31:0]; // @[MulModule.scala 48:31]
  assign bc7_io_y = io_OpB[15:13]; // @[MulModule.scala 49:23]
  assign bc8_io_X = _bc8_io_X_T[31:0]; // @[MulModule.scala 50:31]
  assign bc8_io_y = io_OpB[17:15]; // @[MulModule.scala 51:23]
  assign bc9_io_X = _bc9_io_X_T[31:0]; // @[MulModule.scala 52:31]
  assign bc9_io_y = io_OpB[19:17]; // @[MulModule.scala 53:23]
  assign bc10_io_X = _bc10_io_X_T[31:0]; // @[MulModule.scala 54:32]
  assign bc10_io_y = io_OpB[21:19]; // @[MulModule.scala 55:24]
  assign bc11_io_X = _bc11_io_X_T[31:0]; // @[MulModule.scala 56:32]
  assign bc11_io_y = io_OpB[23:21]; // @[MulModule.scala 57:24]
  assign bc12_io_X = _bc12_io_X_T[31:0]; // @[MulModule.scala 58:32]
  assign bc12_io_y = io_OpB[25:23]; // @[MulModule.scala 59:24]
  assign bc13_io_X = _bc13_io_X_T[31:0]; // @[MulModule.scala 60:32]
  assign bc13_io_y = io_OpB[27:25]; // @[MulModule.scala 61:24]
  assign bc14_io_X = _bc14_io_X_T[31:0]; // @[MulModule.scala 62:32]
  assign bc14_io_y = io_OpB[29:27]; // @[MulModule.scala 63:24]
  assign bc15_io_X = _bc15_io_X_T[31:0]; // @[MulModule.scala 64:32]
  assign bc15_io_y = io_OpB[31:29]; // @[MulModule.scala 65:24]
  assign wt0_io_N = {wt0_io_N_hi,wt0_io_N_lo}; // @[Cat.scala 30:58]
  assign wt0_io_Cin_0 = csReg_0; // @[MulModule.scala 151:19]
  assign wt0_io_Cin_1 = csReg_1; // @[MulModule.scala 152:19]
  assign wt0_io_Cin_2 = csReg_2; // @[MulModule.scala 153:19]
  assign wt0_io_Cin_3 = csReg_3; // @[MulModule.scala 154:19]
  assign wt0_io_Cin_4 = csReg_4; // @[MulModule.scala 155:19]
  assign wt0_io_Cin_5 = csReg_5; // @[MulModule.scala 156:19]
  assign wt0_io_Cin_6 = csReg_6; // @[MulModule.scala 157:19]
  assign wt0_io_Cin_7 = csReg_7; // @[MulModule.scala 158:19]
  assign wt0_io_Cin_8 = csReg_8; // @[MulModule.scala 159:19]
  assign wt0_io_Cin_9 = csReg_9; // @[MulModule.scala 160:19]
  assign wt0_io_Cin_10 = csReg_10; // @[MulModule.scala 161:20]
  assign wt0_io_Cin_11 = csReg_11; // @[MulModule.scala 162:20]
  assign wt0_io_Cin_12 = csReg_12; // @[MulModule.scala 163:20]
  assign wt0_io_Cin_13 = csReg_13; // @[MulModule.scala 164:20]
  assign wt0_io_Cin_14 = csReg_14; // @[MulModule.scala 165:20]
  assign wt1_io_N = {wt1_io_N_hi,wt1_io_N_lo}; // @[Cat.scala 30:58]
  assign wt1_io_Cin_0 = wt0_io_Cout_0; // @[MulModule.scala 167:16]
  assign wt1_io_Cin_1 = wt0_io_Cout_1; // @[MulModule.scala 167:16]
  assign wt1_io_Cin_2 = wt0_io_Cout_2; // @[MulModule.scala 167:16]
  assign wt1_io_Cin_3 = wt0_io_Cout_3; // @[MulModule.scala 167:16]
  assign wt1_io_Cin_4 = wt0_io_Cout_4; // @[MulModule.scala 167:16]
  assign wt1_io_Cin_5 = wt0_io_Cout_5; // @[MulModule.scala 167:16]
  assign wt1_io_Cin_6 = wt0_io_Cout_6; // @[MulModule.scala 167:16]
  assign wt1_io_Cin_7 = wt0_io_Cout_7; // @[MulModule.scala 167:16]
  assign wt1_io_Cin_8 = wt0_io_Cout_8; // @[MulModule.scala 167:16]
  assign wt1_io_Cin_9 = wt0_io_Cout_9; // @[MulModule.scala 167:16]
  assign wt1_io_Cin_10 = wt0_io_Cout_10; // @[MulModule.scala 167:16]
  assign wt1_io_Cin_11 = wt0_io_Cout_11; // @[MulModule.scala 167:16]
  assign wt1_io_Cin_12 = wt0_io_Cout_12; // @[MulModule.scala 167:16]
  assign wt1_io_Cin_13 = wt0_io_Cout_13; // @[MulModule.scala 167:16]
  assign wt1_io_Cin_14 = wt0_io_Cout_14; // @[MulModule.scala 167:16]
  assign wt2_io_N = {wt2_io_N_hi,wt2_io_N_lo}; // @[Cat.scala 30:58]
  assign wt2_io_Cin_0 = wt1_io_Cout_0; // @[MulModule.scala 169:16]
  assign wt2_io_Cin_1 = wt1_io_Cout_1; // @[MulModule.scala 169:16]
  assign wt2_io_Cin_2 = wt1_io_Cout_2; // @[MulModule.scala 169:16]
  assign wt2_io_Cin_3 = wt1_io_Cout_3; // @[MulModule.scala 169:16]
  assign wt2_io_Cin_4 = wt1_io_Cout_4; // @[MulModule.scala 169:16]
  assign wt2_io_Cin_5 = wt1_io_Cout_5; // @[MulModule.scala 169:16]
  assign wt2_io_Cin_6 = wt1_io_Cout_6; // @[MulModule.scala 169:16]
  assign wt2_io_Cin_7 = wt1_io_Cout_7; // @[MulModule.scala 169:16]
  assign wt2_io_Cin_8 = wt1_io_Cout_8; // @[MulModule.scala 169:16]
  assign wt2_io_Cin_9 = wt1_io_Cout_9; // @[MulModule.scala 169:16]
  assign wt2_io_Cin_10 = wt1_io_Cout_10; // @[MulModule.scala 169:16]
  assign wt2_io_Cin_11 = wt1_io_Cout_11; // @[MulModule.scala 169:16]
  assign wt2_io_Cin_12 = wt1_io_Cout_12; // @[MulModule.scala 169:16]
  assign wt2_io_Cin_13 = wt1_io_Cout_13; // @[MulModule.scala 169:16]
  assign wt2_io_Cin_14 = wt1_io_Cout_14; // @[MulModule.scala 169:16]
  assign wt3_io_N = {wt3_io_N_hi,wt3_io_N_lo}; // @[Cat.scala 30:58]
  assign wt3_io_Cin_0 = wt2_io_Cout_0; // @[MulModule.scala 171:16]
  assign wt3_io_Cin_1 = wt2_io_Cout_1; // @[MulModule.scala 171:16]
  assign wt3_io_Cin_2 = wt2_io_Cout_2; // @[MulModule.scala 171:16]
  assign wt3_io_Cin_3 = wt2_io_Cout_3; // @[MulModule.scala 171:16]
  assign wt3_io_Cin_4 = wt2_io_Cout_4; // @[MulModule.scala 171:16]
  assign wt3_io_Cin_5 = wt2_io_Cout_5; // @[MulModule.scala 171:16]
  assign wt3_io_Cin_6 = wt2_io_Cout_6; // @[MulModule.scala 171:16]
  assign wt3_io_Cin_7 = wt2_io_Cout_7; // @[MulModule.scala 171:16]
  assign wt3_io_Cin_8 = wt2_io_Cout_8; // @[MulModule.scala 171:16]
  assign wt3_io_Cin_9 = wt2_io_Cout_9; // @[MulModule.scala 171:16]
  assign wt3_io_Cin_10 = wt2_io_Cout_10; // @[MulModule.scala 171:16]
  assign wt3_io_Cin_11 = wt2_io_Cout_11; // @[MulModule.scala 171:16]
  assign wt3_io_Cin_12 = wt2_io_Cout_12; // @[MulModule.scala 171:16]
  assign wt3_io_Cin_13 = wt2_io_Cout_13; // @[MulModule.scala 171:16]
  assign wt3_io_Cin_14 = wt2_io_Cout_14; // @[MulModule.scala 171:16]
  assign wt4_io_N = {wt4_io_N_hi,wt4_io_N_lo}; // @[Cat.scala 30:58]
  assign wt4_io_Cin_0 = wt3_io_Cout_0; // @[MulModule.scala 173:16]
  assign wt4_io_Cin_1 = wt3_io_Cout_1; // @[MulModule.scala 173:16]
  assign wt4_io_Cin_2 = wt3_io_Cout_2; // @[MulModule.scala 173:16]
  assign wt4_io_Cin_3 = wt3_io_Cout_3; // @[MulModule.scala 173:16]
  assign wt4_io_Cin_4 = wt3_io_Cout_4; // @[MulModule.scala 173:16]
  assign wt4_io_Cin_5 = wt3_io_Cout_5; // @[MulModule.scala 173:16]
  assign wt4_io_Cin_6 = wt3_io_Cout_6; // @[MulModule.scala 173:16]
  assign wt4_io_Cin_7 = wt3_io_Cout_7; // @[MulModule.scala 173:16]
  assign wt4_io_Cin_8 = wt3_io_Cout_8; // @[MulModule.scala 173:16]
  assign wt4_io_Cin_9 = wt3_io_Cout_9; // @[MulModule.scala 173:16]
  assign wt4_io_Cin_10 = wt3_io_Cout_10; // @[MulModule.scala 173:16]
  assign wt4_io_Cin_11 = wt3_io_Cout_11; // @[MulModule.scala 173:16]
  assign wt4_io_Cin_12 = wt3_io_Cout_12; // @[MulModule.scala 173:16]
  assign wt4_io_Cin_13 = wt3_io_Cout_13; // @[MulModule.scala 173:16]
  assign wt4_io_Cin_14 = wt3_io_Cout_14; // @[MulModule.scala 173:16]
  assign wt5_io_N = {wt5_io_N_hi,wt5_io_N_lo}; // @[Cat.scala 30:58]
  assign wt5_io_Cin_0 = wt4_io_Cout_0; // @[MulModule.scala 175:16]
  assign wt5_io_Cin_1 = wt4_io_Cout_1; // @[MulModule.scala 175:16]
  assign wt5_io_Cin_2 = wt4_io_Cout_2; // @[MulModule.scala 175:16]
  assign wt5_io_Cin_3 = wt4_io_Cout_3; // @[MulModule.scala 175:16]
  assign wt5_io_Cin_4 = wt4_io_Cout_4; // @[MulModule.scala 175:16]
  assign wt5_io_Cin_5 = wt4_io_Cout_5; // @[MulModule.scala 175:16]
  assign wt5_io_Cin_6 = wt4_io_Cout_6; // @[MulModule.scala 175:16]
  assign wt5_io_Cin_7 = wt4_io_Cout_7; // @[MulModule.scala 175:16]
  assign wt5_io_Cin_8 = wt4_io_Cout_8; // @[MulModule.scala 175:16]
  assign wt5_io_Cin_9 = wt4_io_Cout_9; // @[MulModule.scala 175:16]
  assign wt5_io_Cin_10 = wt4_io_Cout_10; // @[MulModule.scala 175:16]
  assign wt5_io_Cin_11 = wt4_io_Cout_11; // @[MulModule.scala 175:16]
  assign wt5_io_Cin_12 = wt4_io_Cout_12; // @[MulModule.scala 175:16]
  assign wt5_io_Cin_13 = wt4_io_Cout_13; // @[MulModule.scala 175:16]
  assign wt5_io_Cin_14 = wt4_io_Cout_14; // @[MulModule.scala 175:16]
  assign wt6_io_N = {wt6_io_N_hi,wt6_io_N_lo}; // @[Cat.scala 30:58]
  assign wt6_io_Cin_0 = wt5_io_Cout_0; // @[MulModule.scala 177:16]
  assign wt6_io_Cin_1 = wt5_io_Cout_1; // @[MulModule.scala 177:16]
  assign wt6_io_Cin_2 = wt5_io_Cout_2; // @[MulModule.scala 177:16]
  assign wt6_io_Cin_3 = wt5_io_Cout_3; // @[MulModule.scala 177:16]
  assign wt6_io_Cin_4 = wt5_io_Cout_4; // @[MulModule.scala 177:16]
  assign wt6_io_Cin_5 = wt5_io_Cout_5; // @[MulModule.scala 177:16]
  assign wt6_io_Cin_6 = wt5_io_Cout_6; // @[MulModule.scala 177:16]
  assign wt6_io_Cin_7 = wt5_io_Cout_7; // @[MulModule.scala 177:16]
  assign wt6_io_Cin_8 = wt5_io_Cout_8; // @[MulModule.scala 177:16]
  assign wt6_io_Cin_9 = wt5_io_Cout_9; // @[MulModule.scala 177:16]
  assign wt6_io_Cin_10 = wt5_io_Cout_10; // @[MulModule.scala 177:16]
  assign wt6_io_Cin_11 = wt5_io_Cout_11; // @[MulModule.scala 177:16]
  assign wt6_io_Cin_12 = wt5_io_Cout_12; // @[MulModule.scala 177:16]
  assign wt6_io_Cin_13 = wt5_io_Cout_13; // @[MulModule.scala 177:16]
  assign wt6_io_Cin_14 = wt5_io_Cout_14; // @[MulModule.scala 177:16]
  assign wt7_io_N = {wt7_io_N_hi,wt7_io_N_lo}; // @[Cat.scala 30:58]
  assign wt7_io_Cin_0 = wt6_io_Cout_0; // @[MulModule.scala 179:16]
  assign wt7_io_Cin_1 = wt6_io_Cout_1; // @[MulModule.scala 179:16]
  assign wt7_io_Cin_2 = wt6_io_Cout_2; // @[MulModule.scala 179:16]
  assign wt7_io_Cin_3 = wt6_io_Cout_3; // @[MulModule.scala 179:16]
  assign wt7_io_Cin_4 = wt6_io_Cout_4; // @[MulModule.scala 179:16]
  assign wt7_io_Cin_5 = wt6_io_Cout_5; // @[MulModule.scala 179:16]
  assign wt7_io_Cin_6 = wt6_io_Cout_6; // @[MulModule.scala 179:16]
  assign wt7_io_Cin_7 = wt6_io_Cout_7; // @[MulModule.scala 179:16]
  assign wt7_io_Cin_8 = wt6_io_Cout_8; // @[MulModule.scala 179:16]
  assign wt7_io_Cin_9 = wt6_io_Cout_9; // @[MulModule.scala 179:16]
  assign wt7_io_Cin_10 = wt6_io_Cout_10; // @[MulModule.scala 179:16]
  assign wt7_io_Cin_11 = wt6_io_Cout_11; // @[MulModule.scala 179:16]
  assign wt7_io_Cin_12 = wt6_io_Cout_12; // @[MulModule.scala 179:16]
  assign wt7_io_Cin_13 = wt6_io_Cout_13; // @[MulModule.scala 179:16]
  assign wt7_io_Cin_14 = wt6_io_Cout_14; // @[MulModule.scala 179:16]
  assign wt8_io_N = {wt8_io_N_hi,wt8_io_N_lo}; // @[Cat.scala 30:58]
  assign wt8_io_Cin_0 = wt7_io_Cout_0; // @[MulModule.scala 181:16]
  assign wt8_io_Cin_1 = wt7_io_Cout_1; // @[MulModule.scala 181:16]
  assign wt8_io_Cin_2 = wt7_io_Cout_2; // @[MulModule.scala 181:16]
  assign wt8_io_Cin_3 = wt7_io_Cout_3; // @[MulModule.scala 181:16]
  assign wt8_io_Cin_4 = wt7_io_Cout_4; // @[MulModule.scala 181:16]
  assign wt8_io_Cin_5 = wt7_io_Cout_5; // @[MulModule.scala 181:16]
  assign wt8_io_Cin_6 = wt7_io_Cout_6; // @[MulModule.scala 181:16]
  assign wt8_io_Cin_7 = wt7_io_Cout_7; // @[MulModule.scala 181:16]
  assign wt8_io_Cin_8 = wt7_io_Cout_8; // @[MulModule.scala 181:16]
  assign wt8_io_Cin_9 = wt7_io_Cout_9; // @[MulModule.scala 181:16]
  assign wt8_io_Cin_10 = wt7_io_Cout_10; // @[MulModule.scala 181:16]
  assign wt8_io_Cin_11 = wt7_io_Cout_11; // @[MulModule.scala 181:16]
  assign wt8_io_Cin_12 = wt7_io_Cout_12; // @[MulModule.scala 181:16]
  assign wt8_io_Cin_13 = wt7_io_Cout_13; // @[MulModule.scala 181:16]
  assign wt8_io_Cin_14 = wt7_io_Cout_14; // @[MulModule.scala 181:16]
  assign wt9_io_N = {wt9_io_N_hi,wt9_io_N_lo}; // @[Cat.scala 30:58]
  assign wt9_io_Cin_0 = wt8_io_Cout_0; // @[MulModule.scala 183:16]
  assign wt9_io_Cin_1 = wt8_io_Cout_1; // @[MulModule.scala 183:16]
  assign wt9_io_Cin_2 = wt8_io_Cout_2; // @[MulModule.scala 183:16]
  assign wt9_io_Cin_3 = wt8_io_Cout_3; // @[MulModule.scala 183:16]
  assign wt9_io_Cin_4 = wt8_io_Cout_4; // @[MulModule.scala 183:16]
  assign wt9_io_Cin_5 = wt8_io_Cout_5; // @[MulModule.scala 183:16]
  assign wt9_io_Cin_6 = wt8_io_Cout_6; // @[MulModule.scala 183:16]
  assign wt9_io_Cin_7 = wt8_io_Cout_7; // @[MulModule.scala 183:16]
  assign wt9_io_Cin_8 = wt8_io_Cout_8; // @[MulModule.scala 183:16]
  assign wt9_io_Cin_9 = wt8_io_Cout_9; // @[MulModule.scala 183:16]
  assign wt9_io_Cin_10 = wt8_io_Cout_10; // @[MulModule.scala 183:16]
  assign wt9_io_Cin_11 = wt8_io_Cout_11; // @[MulModule.scala 183:16]
  assign wt9_io_Cin_12 = wt8_io_Cout_12; // @[MulModule.scala 183:16]
  assign wt9_io_Cin_13 = wt8_io_Cout_13; // @[MulModule.scala 183:16]
  assign wt9_io_Cin_14 = wt8_io_Cout_14; // @[MulModule.scala 183:16]
  assign wt10_io_N = {wt10_io_N_hi,wt10_io_N_lo}; // @[Cat.scala 30:58]
  assign wt10_io_Cin_0 = wt9_io_Cout_0; // @[MulModule.scala 185:17]
  assign wt10_io_Cin_1 = wt9_io_Cout_1; // @[MulModule.scala 185:17]
  assign wt10_io_Cin_2 = wt9_io_Cout_2; // @[MulModule.scala 185:17]
  assign wt10_io_Cin_3 = wt9_io_Cout_3; // @[MulModule.scala 185:17]
  assign wt10_io_Cin_4 = wt9_io_Cout_4; // @[MulModule.scala 185:17]
  assign wt10_io_Cin_5 = wt9_io_Cout_5; // @[MulModule.scala 185:17]
  assign wt10_io_Cin_6 = wt9_io_Cout_6; // @[MulModule.scala 185:17]
  assign wt10_io_Cin_7 = wt9_io_Cout_7; // @[MulModule.scala 185:17]
  assign wt10_io_Cin_8 = wt9_io_Cout_8; // @[MulModule.scala 185:17]
  assign wt10_io_Cin_9 = wt9_io_Cout_9; // @[MulModule.scala 185:17]
  assign wt10_io_Cin_10 = wt9_io_Cout_10; // @[MulModule.scala 185:17]
  assign wt10_io_Cin_11 = wt9_io_Cout_11; // @[MulModule.scala 185:17]
  assign wt10_io_Cin_12 = wt9_io_Cout_12; // @[MulModule.scala 185:17]
  assign wt10_io_Cin_13 = wt9_io_Cout_13; // @[MulModule.scala 185:17]
  assign wt10_io_Cin_14 = wt9_io_Cout_14; // @[MulModule.scala 185:17]
  assign wt11_io_N = {wt11_io_N_hi,wt11_io_N_lo}; // @[Cat.scala 30:58]
  assign wt11_io_Cin_0 = wt10_io_Cout_0; // @[MulModule.scala 187:17]
  assign wt11_io_Cin_1 = wt10_io_Cout_1; // @[MulModule.scala 187:17]
  assign wt11_io_Cin_2 = wt10_io_Cout_2; // @[MulModule.scala 187:17]
  assign wt11_io_Cin_3 = wt10_io_Cout_3; // @[MulModule.scala 187:17]
  assign wt11_io_Cin_4 = wt10_io_Cout_4; // @[MulModule.scala 187:17]
  assign wt11_io_Cin_5 = wt10_io_Cout_5; // @[MulModule.scala 187:17]
  assign wt11_io_Cin_6 = wt10_io_Cout_6; // @[MulModule.scala 187:17]
  assign wt11_io_Cin_7 = wt10_io_Cout_7; // @[MulModule.scala 187:17]
  assign wt11_io_Cin_8 = wt10_io_Cout_8; // @[MulModule.scala 187:17]
  assign wt11_io_Cin_9 = wt10_io_Cout_9; // @[MulModule.scala 187:17]
  assign wt11_io_Cin_10 = wt10_io_Cout_10; // @[MulModule.scala 187:17]
  assign wt11_io_Cin_11 = wt10_io_Cout_11; // @[MulModule.scala 187:17]
  assign wt11_io_Cin_12 = wt10_io_Cout_12; // @[MulModule.scala 187:17]
  assign wt11_io_Cin_13 = wt10_io_Cout_13; // @[MulModule.scala 187:17]
  assign wt11_io_Cin_14 = wt10_io_Cout_14; // @[MulModule.scala 187:17]
  assign wt12_io_N = {wt12_io_N_hi,wt12_io_N_lo}; // @[Cat.scala 30:58]
  assign wt12_io_Cin_0 = wt11_io_Cout_0; // @[MulModule.scala 189:17]
  assign wt12_io_Cin_1 = wt11_io_Cout_1; // @[MulModule.scala 189:17]
  assign wt12_io_Cin_2 = wt11_io_Cout_2; // @[MulModule.scala 189:17]
  assign wt12_io_Cin_3 = wt11_io_Cout_3; // @[MulModule.scala 189:17]
  assign wt12_io_Cin_4 = wt11_io_Cout_4; // @[MulModule.scala 189:17]
  assign wt12_io_Cin_5 = wt11_io_Cout_5; // @[MulModule.scala 189:17]
  assign wt12_io_Cin_6 = wt11_io_Cout_6; // @[MulModule.scala 189:17]
  assign wt12_io_Cin_7 = wt11_io_Cout_7; // @[MulModule.scala 189:17]
  assign wt12_io_Cin_8 = wt11_io_Cout_8; // @[MulModule.scala 189:17]
  assign wt12_io_Cin_9 = wt11_io_Cout_9; // @[MulModule.scala 189:17]
  assign wt12_io_Cin_10 = wt11_io_Cout_10; // @[MulModule.scala 189:17]
  assign wt12_io_Cin_11 = wt11_io_Cout_11; // @[MulModule.scala 189:17]
  assign wt12_io_Cin_12 = wt11_io_Cout_12; // @[MulModule.scala 189:17]
  assign wt12_io_Cin_13 = wt11_io_Cout_13; // @[MulModule.scala 189:17]
  assign wt12_io_Cin_14 = wt11_io_Cout_14; // @[MulModule.scala 189:17]
  assign wt13_io_N = {wt13_io_N_hi,wt13_io_N_lo}; // @[Cat.scala 30:58]
  assign wt13_io_Cin_0 = wt12_io_Cout_0; // @[MulModule.scala 191:17]
  assign wt13_io_Cin_1 = wt12_io_Cout_1; // @[MulModule.scala 191:17]
  assign wt13_io_Cin_2 = wt12_io_Cout_2; // @[MulModule.scala 191:17]
  assign wt13_io_Cin_3 = wt12_io_Cout_3; // @[MulModule.scala 191:17]
  assign wt13_io_Cin_4 = wt12_io_Cout_4; // @[MulModule.scala 191:17]
  assign wt13_io_Cin_5 = wt12_io_Cout_5; // @[MulModule.scala 191:17]
  assign wt13_io_Cin_6 = wt12_io_Cout_6; // @[MulModule.scala 191:17]
  assign wt13_io_Cin_7 = wt12_io_Cout_7; // @[MulModule.scala 191:17]
  assign wt13_io_Cin_8 = wt12_io_Cout_8; // @[MulModule.scala 191:17]
  assign wt13_io_Cin_9 = wt12_io_Cout_9; // @[MulModule.scala 191:17]
  assign wt13_io_Cin_10 = wt12_io_Cout_10; // @[MulModule.scala 191:17]
  assign wt13_io_Cin_11 = wt12_io_Cout_11; // @[MulModule.scala 191:17]
  assign wt13_io_Cin_12 = wt12_io_Cout_12; // @[MulModule.scala 191:17]
  assign wt13_io_Cin_13 = wt12_io_Cout_13; // @[MulModule.scala 191:17]
  assign wt13_io_Cin_14 = wt12_io_Cout_14; // @[MulModule.scala 191:17]
  assign wt14_io_N = {wt14_io_N_hi,wt14_io_N_lo}; // @[Cat.scala 30:58]
  assign wt14_io_Cin_0 = wt13_io_Cout_0; // @[MulModule.scala 193:17]
  assign wt14_io_Cin_1 = wt13_io_Cout_1; // @[MulModule.scala 193:17]
  assign wt14_io_Cin_2 = wt13_io_Cout_2; // @[MulModule.scala 193:17]
  assign wt14_io_Cin_3 = wt13_io_Cout_3; // @[MulModule.scala 193:17]
  assign wt14_io_Cin_4 = wt13_io_Cout_4; // @[MulModule.scala 193:17]
  assign wt14_io_Cin_5 = wt13_io_Cout_5; // @[MulModule.scala 193:17]
  assign wt14_io_Cin_6 = wt13_io_Cout_6; // @[MulModule.scala 193:17]
  assign wt14_io_Cin_7 = wt13_io_Cout_7; // @[MulModule.scala 193:17]
  assign wt14_io_Cin_8 = wt13_io_Cout_8; // @[MulModule.scala 193:17]
  assign wt14_io_Cin_9 = wt13_io_Cout_9; // @[MulModule.scala 193:17]
  assign wt14_io_Cin_10 = wt13_io_Cout_10; // @[MulModule.scala 193:17]
  assign wt14_io_Cin_11 = wt13_io_Cout_11; // @[MulModule.scala 193:17]
  assign wt14_io_Cin_12 = wt13_io_Cout_12; // @[MulModule.scala 193:17]
  assign wt14_io_Cin_13 = wt13_io_Cout_13; // @[MulModule.scala 193:17]
  assign wt14_io_Cin_14 = wt13_io_Cout_14; // @[MulModule.scala 193:17]
  assign wt15_io_N = {wt15_io_N_hi,wt15_io_N_lo}; // @[Cat.scala 30:58]
  assign wt15_io_Cin_0 = wt14_io_Cout_0; // @[MulModule.scala 195:17]
  assign wt15_io_Cin_1 = wt14_io_Cout_1; // @[MulModule.scala 195:17]
  assign wt15_io_Cin_2 = wt14_io_Cout_2; // @[MulModule.scala 195:17]
  assign wt15_io_Cin_3 = wt14_io_Cout_3; // @[MulModule.scala 195:17]
  assign wt15_io_Cin_4 = wt14_io_Cout_4; // @[MulModule.scala 195:17]
  assign wt15_io_Cin_5 = wt14_io_Cout_5; // @[MulModule.scala 195:17]
  assign wt15_io_Cin_6 = wt14_io_Cout_6; // @[MulModule.scala 195:17]
  assign wt15_io_Cin_7 = wt14_io_Cout_7; // @[MulModule.scala 195:17]
  assign wt15_io_Cin_8 = wt14_io_Cout_8; // @[MulModule.scala 195:17]
  assign wt15_io_Cin_9 = wt14_io_Cout_9; // @[MulModule.scala 195:17]
  assign wt15_io_Cin_10 = wt14_io_Cout_10; // @[MulModule.scala 195:17]
  assign wt15_io_Cin_11 = wt14_io_Cout_11; // @[MulModule.scala 195:17]
  assign wt15_io_Cin_12 = wt14_io_Cout_12; // @[MulModule.scala 195:17]
  assign wt15_io_Cin_13 = wt14_io_Cout_13; // @[MulModule.scala 195:17]
  assign wt15_io_Cin_14 = wt14_io_Cout_14; // @[MulModule.scala 195:17]
  assign wt16_io_N = {wt16_io_N_hi,wt16_io_N_lo}; // @[Cat.scala 30:58]
  assign wt16_io_Cin_0 = wt15_io_Cout_0; // @[MulModule.scala 197:17]
  assign wt16_io_Cin_1 = wt15_io_Cout_1; // @[MulModule.scala 197:17]
  assign wt16_io_Cin_2 = wt15_io_Cout_2; // @[MulModule.scala 197:17]
  assign wt16_io_Cin_3 = wt15_io_Cout_3; // @[MulModule.scala 197:17]
  assign wt16_io_Cin_4 = wt15_io_Cout_4; // @[MulModule.scala 197:17]
  assign wt16_io_Cin_5 = wt15_io_Cout_5; // @[MulModule.scala 197:17]
  assign wt16_io_Cin_6 = wt15_io_Cout_6; // @[MulModule.scala 197:17]
  assign wt16_io_Cin_7 = wt15_io_Cout_7; // @[MulModule.scala 197:17]
  assign wt16_io_Cin_8 = wt15_io_Cout_8; // @[MulModule.scala 197:17]
  assign wt16_io_Cin_9 = wt15_io_Cout_9; // @[MulModule.scala 197:17]
  assign wt16_io_Cin_10 = wt15_io_Cout_10; // @[MulModule.scala 197:17]
  assign wt16_io_Cin_11 = wt15_io_Cout_11; // @[MulModule.scala 197:17]
  assign wt16_io_Cin_12 = wt15_io_Cout_12; // @[MulModule.scala 197:17]
  assign wt16_io_Cin_13 = wt15_io_Cout_13; // @[MulModule.scala 197:17]
  assign wt16_io_Cin_14 = wt15_io_Cout_14; // @[MulModule.scala 197:17]
  assign wt17_io_N = {wt17_io_N_hi,wt17_io_N_lo}; // @[Cat.scala 30:58]
  assign wt17_io_Cin_0 = wt16_io_Cout_0; // @[MulModule.scala 199:17]
  assign wt17_io_Cin_1 = wt16_io_Cout_1; // @[MulModule.scala 199:17]
  assign wt17_io_Cin_2 = wt16_io_Cout_2; // @[MulModule.scala 199:17]
  assign wt17_io_Cin_3 = wt16_io_Cout_3; // @[MulModule.scala 199:17]
  assign wt17_io_Cin_4 = wt16_io_Cout_4; // @[MulModule.scala 199:17]
  assign wt17_io_Cin_5 = wt16_io_Cout_5; // @[MulModule.scala 199:17]
  assign wt17_io_Cin_6 = wt16_io_Cout_6; // @[MulModule.scala 199:17]
  assign wt17_io_Cin_7 = wt16_io_Cout_7; // @[MulModule.scala 199:17]
  assign wt17_io_Cin_8 = wt16_io_Cout_8; // @[MulModule.scala 199:17]
  assign wt17_io_Cin_9 = wt16_io_Cout_9; // @[MulModule.scala 199:17]
  assign wt17_io_Cin_10 = wt16_io_Cout_10; // @[MulModule.scala 199:17]
  assign wt17_io_Cin_11 = wt16_io_Cout_11; // @[MulModule.scala 199:17]
  assign wt17_io_Cin_12 = wt16_io_Cout_12; // @[MulModule.scala 199:17]
  assign wt17_io_Cin_13 = wt16_io_Cout_13; // @[MulModule.scala 199:17]
  assign wt17_io_Cin_14 = wt16_io_Cout_14; // @[MulModule.scala 199:17]
  assign wt18_io_N = {wt18_io_N_hi,wt18_io_N_lo}; // @[Cat.scala 30:58]
  assign wt18_io_Cin_0 = wt17_io_Cout_0; // @[MulModule.scala 201:17]
  assign wt18_io_Cin_1 = wt17_io_Cout_1; // @[MulModule.scala 201:17]
  assign wt18_io_Cin_2 = wt17_io_Cout_2; // @[MulModule.scala 201:17]
  assign wt18_io_Cin_3 = wt17_io_Cout_3; // @[MulModule.scala 201:17]
  assign wt18_io_Cin_4 = wt17_io_Cout_4; // @[MulModule.scala 201:17]
  assign wt18_io_Cin_5 = wt17_io_Cout_5; // @[MulModule.scala 201:17]
  assign wt18_io_Cin_6 = wt17_io_Cout_6; // @[MulModule.scala 201:17]
  assign wt18_io_Cin_7 = wt17_io_Cout_7; // @[MulModule.scala 201:17]
  assign wt18_io_Cin_8 = wt17_io_Cout_8; // @[MulModule.scala 201:17]
  assign wt18_io_Cin_9 = wt17_io_Cout_9; // @[MulModule.scala 201:17]
  assign wt18_io_Cin_10 = wt17_io_Cout_10; // @[MulModule.scala 201:17]
  assign wt18_io_Cin_11 = wt17_io_Cout_11; // @[MulModule.scala 201:17]
  assign wt18_io_Cin_12 = wt17_io_Cout_12; // @[MulModule.scala 201:17]
  assign wt18_io_Cin_13 = wt17_io_Cout_13; // @[MulModule.scala 201:17]
  assign wt18_io_Cin_14 = wt17_io_Cout_14; // @[MulModule.scala 201:17]
  assign wt19_io_N = {wt19_io_N_hi,wt19_io_N_lo}; // @[Cat.scala 30:58]
  assign wt19_io_Cin_0 = wt18_io_Cout_0; // @[MulModule.scala 203:17]
  assign wt19_io_Cin_1 = wt18_io_Cout_1; // @[MulModule.scala 203:17]
  assign wt19_io_Cin_2 = wt18_io_Cout_2; // @[MulModule.scala 203:17]
  assign wt19_io_Cin_3 = wt18_io_Cout_3; // @[MulModule.scala 203:17]
  assign wt19_io_Cin_4 = wt18_io_Cout_4; // @[MulModule.scala 203:17]
  assign wt19_io_Cin_5 = wt18_io_Cout_5; // @[MulModule.scala 203:17]
  assign wt19_io_Cin_6 = wt18_io_Cout_6; // @[MulModule.scala 203:17]
  assign wt19_io_Cin_7 = wt18_io_Cout_7; // @[MulModule.scala 203:17]
  assign wt19_io_Cin_8 = wt18_io_Cout_8; // @[MulModule.scala 203:17]
  assign wt19_io_Cin_9 = wt18_io_Cout_9; // @[MulModule.scala 203:17]
  assign wt19_io_Cin_10 = wt18_io_Cout_10; // @[MulModule.scala 203:17]
  assign wt19_io_Cin_11 = wt18_io_Cout_11; // @[MulModule.scala 203:17]
  assign wt19_io_Cin_12 = wt18_io_Cout_12; // @[MulModule.scala 203:17]
  assign wt19_io_Cin_13 = wt18_io_Cout_13; // @[MulModule.scala 203:17]
  assign wt19_io_Cin_14 = wt18_io_Cout_14; // @[MulModule.scala 203:17]
  assign wt20_io_N = {wt20_io_N_hi,wt20_io_N_lo}; // @[Cat.scala 30:58]
  assign wt20_io_Cin_0 = wt19_io_Cout_0; // @[MulModule.scala 205:17]
  assign wt20_io_Cin_1 = wt19_io_Cout_1; // @[MulModule.scala 205:17]
  assign wt20_io_Cin_2 = wt19_io_Cout_2; // @[MulModule.scala 205:17]
  assign wt20_io_Cin_3 = wt19_io_Cout_3; // @[MulModule.scala 205:17]
  assign wt20_io_Cin_4 = wt19_io_Cout_4; // @[MulModule.scala 205:17]
  assign wt20_io_Cin_5 = wt19_io_Cout_5; // @[MulModule.scala 205:17]
  assign wt20_io_Cin_6 = wt19_io_Cout_6; // @[MulModule.scala 205:17]
  assign wt20_io_Cin_7 = wt19_io_Cout_7; // @[MulModule.scala 205:17]
  assign wt20_io_Cin_8 = wt19_io_Cout_8; // @[MulModule.scala 205:17]
  assign wt20_io_Cin_9 = wt19_io_Cout_9; // @[MulModule.scala 205:17]
  assign wt20_io_Cin_10 = wt19_io_Cout_10; // @[MulModule.scala 205:17]
  assign wt20_io_Cin_11 = wt19_io_Cout_11; // @[MulModule.scala 205:17]
  assign wt20_io_Cin_12 = wt19_io_Cout_12; // @[MulModule.scala 205:17]
  assign wt20_io_Cin_13 = wt19_io_Cout_13; // @[MulModule.scala 205:17]
  assign wt20_io_Cin_14 = wt19_io_Cout_14; // @[MulModule.scala 205:17]
  assign wt21_io_N = {wt21_io_N_hi,wt21_io_N_lo}; // @[Cat.scala 30:58]
  assign wt21_io_Cin_0 = wt20_io_Cout_0; // @[MulModule.scala 207:17]
  assign wt21_io_Cin_1 = wt20_io_Cout_1; // @[MulModule.scala 207:17]
  assign wt21_io_Cin_2 = wt20_io_Cout_2; // @[MulModule.scala 207:17]
  assign wt21_io_Cin_3 = wt20_io_Cout_3; // @[MulModule.scala 207:17]
  assign wt21_io_Cin_4 = wt20_io_Cout_4; // @[MulModule.scala 207:17]
  assign wt21_io_Cin_5 = wt20_io_Cout_5; // @[MulModule.scala 207:17]
  assign wt21_io_Cin_6 = wt20_io_Cout_6; // @[MulModule.scala 207:17]
  assign wt21_io_Cin_7 = wt20_io_Cout_7; // @[MulModule.scala 207:17]
  assign wt21_io_Cin_8 = wt20_io_Cout_8; // @[MulModule.scala 207:17]
  assign wt21_io_Cin_9 = wt20_io_Cout_9; // @[MulModule.scala 207:17]
  assign wt21_io_Cin_10 = wt20_io_Cout_10; // @[MulModule.scala 207:17]
  assign wt21_io_Cin_11 = wt20_io_Cout_11; // @[MulModule.scala 207:17]
  assign wt21_io_Cin_12 = wt20_io_Cout_12; // @[MulModule.scala 207:17]
  assign wt21_io_Cin_13 = wt20_io_Cout_13; // @[MulModule.scala 207:17]
  assign wt21_io_Cin_14 = wt20_io_Cout_14; // @[MulModule.scala 207:17]
  assign wt22_io_N = {wt22_io_N_hi,wt22_io_N_lo}; // @[Cat.scala 30:58]
  assign wt22_io_Cin_0 = wt21_io_Cout_0; // @[MulModule.scala 209:17]
  assign wt22_io_Cin_1 = wt21_io_Cout_1; // @[MulModule.scala 209:17]
  assign wt22_io_Cin_2 = wt21_io_Cout_2; // @[MulModule.scala 209:17]
  assign wt22_io_Cin_3 = wt21_io_Cout_3; // @[MulModule.scala 209:17]
  assign wt22_io_Cin_4 = wt21_io_Cout_4; // @[MulModule.scala 209:17]
  assign wt22_io_Cin_5 = wt21_io_Cout_5; // @[MulModule.scala 209:17]
  assign wt22_io_Cin_6 = wt21_io_Cout_6; // @[MulModule.scala 209:17]
  assign wt22_io_Cin_7 = wt21_io_Cout_7; // @[MulModule.scala 209:17]
  assign wt22_io_Cin_8 = wt21_io_Cout_8; // @[MulModule.scala 209:17]
  assign wt22_io_Cin_9 = wt21_io_Cout_9; // @[MulModule.scala 209:17]
  assign wt22_io_Cin_10 = wt21_io_Cout_10; // @[MulModule.scala 209:17]
  assign wt22_io_Cin_11 = wt21_io_Cout_11; // @[MulModule.scala 209:17]
  assign wt22_io_Cin_12 = wt21_io_Cout_12; // @[MulModule.scala 209:17]
  assign wt22_io_Cin_13 = wt21_io_Cout_13; // @[MulModule.scala 209:17]
  assign wt22_io_Cin_14 = wt21_io_Cout_14; // @[MulModule.scala 209:17]
  assign wt23_io_N = {wt23_io_N_hi,wt23_io_N_lo}; // @[Cat.scala 30:58]
  assign wt23_io_Cin_0 = wt22_io_Cout_0; // @[MulModule.scala 211:17]
  assign wt23_io_Cin_1 = wt22_io_Cout_1; // @[MulModule.scala 211:17]
  assign wt23_io_Cin_2 = wt22_io_Cout_2; // @[MulModule.scala 211:17]
  assign wt23_io_Cin_3 = wt22_io_Cout_3; // @[MulModule.scala 211:17]
  assign wt23_io_Cin_4 = wt22_io_Cout_4; // @[MulModule.scala 211:17]
  assign wt23_io_Cin_5 = wt22_io_Cout_5; // @[MulModule.scala 211:17]
  assign wt23_io_Cin_6 = wt22_io_Cout_6; // @[MulModule.scala 211:17]
  assign wt23_io_Cin_7 = wt22_io_Cout_7; // @[MulModule.scala 211:17]
  assign wt23_io_Cin_8 = wt22_io_Cout_8; // @[MulModule.scala 211:17]
  assign wt23_io_Cin_9 = wt22_io_Cout_9; // @[MulModule.scala 211:17]
  assign wt23_io_Cin_10 = wt22_io_Cout_10; // @[MulModule.scala 211:17]
  assign wt23_io_Cin_11 = wt22_io_Cout_11; // @[MulModule.scala 211:17]
  assign wt23_io_Cin_12 = wt22_io_Cout_12; // @[MulModule.scala 211:17]
  assign wt23_io_Cin_13 = wt22_io_Cout_13; // @[MulModule.scala 211:17]
  assign wt23_io_Cin_14 = wt22_io_Cout_14; // @[MulModule.scala 211:17]
  assign wt24_io_N = {wt24_io_N_hi,wt24_io_N_lo}; // @[Cat.scala 30:58]
  assign wt24_io_Cin_0 = wt23_io_Cout_0; // @[MulModule.scala 213:17]
  assign wt24_io_Cin_1 = wt23_io_Cout_1; // @[MulModule.scala 213:17]
  assign wt24_io_Cin_2 = wt23_io_Cout_2; // @[MulModule.scala 213:17]
  assign wt24_io_Cin_3 = wt23_io_Cout_3; // @[MulModule.scala 213:17]
  assign wt24_io_Cin_4 = wt23_io_Cout_4; // @[MulModule.scala 213:17]
  assign wt24_io_Cin_5 = wt23_io_Cout_5; // @[MulModule.scala 213:17]
  assign wt24_io_Cin_6 = wt23_io_Cout_6; // @[MulModule.scala 213:17]
  assign wt24_io_Cin_7 = wt23_io_Cout_7; // @[MulModule.scala 213:17]
  assign wt24_io_Cin_8 = wt23_io_Cout_8; // @[MulModule.scala 213:17]
  assign wt24_io_Cin_9 = wt23_io_Cout_9; // @[MulModule.scala 213:17]
  assign wt24_io_Cin_10 = wt23_io_Cout_10; // @[MulModule.scala 213:17]
  assign wt24_io_Cin_11 = wt23_io_Cout_11; // @[MulModule.scala 213:17]
  assign wt24_io_Cin_12 = wt23_io_Cout_12; // @[MulModule.scala 213:17]
  assign wt24_io_Cin_13 = wt23_io_Cout_13; // @[MulModule.scala 213:17]
  assign wt24_io_Cin_14 = wt23_io_Cout_14; // @[MulModule.scala 213:17]
  assign wt25_io_N = {wt25_io_N_hi,wt25_io_N_lo}; // @[Cat.scala 30:58]
  assign wt25_io_Cin_0 = wt24_io_Cout_0; // @[MulModule.scala 215:17]
  assign wt25_io_Cin_1 = wt24_io_Cout_1; // @[MulModule.scala 215:17]
  assign wt25_io_Cin_2 = wt24_io_Cout_2; // @[MulModule.scala 215:17]
  assign wt25_io_Cin_3 = wt24_io_Cout_3; // @[MulModule.scala 215:17]
  assign wt25_io_Cin_4 = wt24_io_Cout_4; // @[MulModule.scala 215:17]
  assign wt25_io_Cin_5 = wt24_io_Cout_5; // @[MulModule.scala 215:17]
  assign wt25_io_Cin_6 = wt24_io_Cout_6; // @[MulModule.scala 215:17]
  assign wt25_io_Cin_7 = wt24_io_Cout_7; // @[MulModule.scala 215:17]
  assign wt25_io_Cin_8 = wt24_io_Cout_8; // @[MulModule.scala 215:17]
  assign wt25_io_Cin_9 = wt24_io_Cout_9; // @[MulModule.scala 215:17]
  assign wt25_io_Cin_10 = wt24_io_Cout_10; // @[MulModule.scala 215:17]
  assign wt25_io_Cin_11 = wt24_io_Cout_11; // @[MulModule.scala 215:17]
  assign wt25_io_Cin_12 = wt24_io_Cout_12; // @[MulModule.scala 215:17]
  assign wt25_io_Cin_13 = wt24_io_Cout_13; // @[MulModule.scala 215:17]
  assign wt25_io_Cin_14 = wt24_io_Cout_14; // @[MulModule.scala 215:17]
  assign wt26_io_N = {wt26_io_N_hi,wt26_io_N_lo}; // @[Cat.scala 30:58]
  assign wt26_io_Cin_0 = wt25_io_Cout_0; // @[MulModule.scala 217:17]
  assign wt26_io_Cin_1 = wt25_io_Cout_1; // @[MulModule.scala 217:17]
  assign wt26_io_Cin_2 = wt25_io_Cout_2; // @[MulModule.scala 217:17]
  assign wt26_io_Cin_3 = wt25_io_Cout_3; // @[MulModule.scala 217:17]
  assign wt26_io_Cin_4 = wt25_io_Cout_4; // @[MulModule.scala 217:17]
  assign wt26_io_Cin_5 = wt25_io_Cout_5; // @[MulModule.scala 217:17]
  assign wt26_io_Cin_6 = wt25_io_Cout_6; // @[MulModule.scala 217:17]
  assign wt26_io_Cin_7 = wt25_io_Cout_7; // @[MulModule.scala 217:17]
  assign wt26_io_Cin_8 = wt25_io_Cout_8; // @[MulModule.scala 217:17]
  assign wt26_io_Cin_9 = wt25_io_Cout_9; // @[MulModule.scala 217:17]
  assign wt26_io_Cin_10 = wt25_io_Cout_10; // @[MulModule.scala 217:17]
  assign wt26_io_Cin_11 = wt25_io_Cout_11; // @[MulModule.scala 217:17]
  assign wt26_io_Cin_12 = wt25_io_Cout_12; // @[MulModule.scala 217:17]
  assign wt26_io_Cin_13 = wt25_io_Cout_13; // @[MulModule.scala 217:17]
  assign wt26_io_Cin_14 = wt25_io_Cout_14; // @[MulModule.scala 217:17]
  assign wt27_io_N = {wt27_io_N_hi,wt27_io_N_lo}; // @[Cat.scala 30:58]
  assign wt27_io_Cin_0 = wt26_io_Cout_0; // @[MulModule.scala 219:17]
  assign wt27_io_Cin_1 = wt26_io_Cout_1; // @[MulModule.scala 219:17]
  assign wt27_io_Cin_2 = wt26_io_Cout_2; // @[MulModule.scala 219:17]
  assign wt27_io_Cin_3 = wt26_io_Cout_3; // @[MulModule.scala 219:17]
  assign wt27_io_Cin_4 = wt26_io_Cout_4; // @[MulModule.scala 219:17]
  assign wt27_io_Cin_5 = wt26_io_Cout_5; // @[MulModule.scala 219:17]
  assign wt27_io_Cin_6 = wt26_io_Cout_6; // @[MulModule.scala 219:17]
  assign wt27_io_Cin_7 = wt26_io_Cout_7; // @[MulModule.scala 219:17]
  assign wt27_io_Cin_8 = wt26_io_Cout_8; // @[MulModule.scala 219:17]
  assign wt27_io_Cin_9 = wt26_io_Cout_9; // @[MulModule.scala 219:17]
  assign wt27_io_Cin_10 = wt26_io_Cout_10; // @[MulModule.scala 219:17]
  assign wt27_io_Cin_11 = wt26_io_Cout_11; // @[MulModule.scala 219:17]
  assign wt27_io_Cin_12 = wt26_io_Cout_12; // @[MulModule.scala 219:17]
  assign wt27_io_Cin_13 = wt26_io_Cout_13; // @[MulModule.scala 219:17]
  assign wt27_io_Cin_14 = wt26_io_Cout_14; // @[MulModule.scala 219:17]
  assign wt28_io_N = {wt28_io_N_hi,wt28_io_N_lo}; // @[Cat.scala 30:58]
  assign wt28_io_Cin_0 = wt27_io_Cout_0; // @[MulModule.scala 221:17]
  assign wt28_io_Cin_1 = wt27_io_Cout_1; // @[MulModule.scala 221:17]
  assign wt28_io_Cin_2 = wt27_io_Cout_2; // @[MulModule.scala 221:17]
  assign wt28_io_Cin_3 = wt27_io_Cout_3; // @[MulModule.scala 221:17]
  assign wt28_io_Cin_4 = wt27_io_Cout_4; // @[MulModule.scala 221:17]
  assign wt28_io_Cin_5 = wt27_io_Cout_5; // @[MulModule.scala 221:17]
  assign wt28_io_Cin_6 = wt27_io_Cout_6; // @[MulModule.scala 221:17]
  assign wt28_io_Cin_7 = wt27_io_Cout_7; // @[MulModule.scala 221:17]
  assign wt28_io_Cin_8 = wt27_io_Cout_8; // @[MulModule.scala 221:17]
  assign wt28_io_Cin_9 = wt27_io_Cout_9; // @[MulModule.scala 221:17]
  assign wt28_io_Cin_10 = wt27_io_Cout_10; // @[MulModule.scala 221:17]
  assign wt28_io_Cin_11 = wt27_io_Cout_11; // @[MulModule.scala 221:17]
  assign wt28_io_Cin_12 = wt27_io_Cout_12; // @[MulModule.scala 221:17]
  assign wt28_io_Cin_13 = wt27_io_Cout_13; // @[MulModule.scala 221:17]
  assign wt28_io_Cin_14 = wt27_io_Cout_14; // @[MulModule.scala 221:17]
  assign wt29_io_N = {wt29_io_N_hi,wt29_io_N_lo}; // @[Cat.scala 30:58]
  assign wt29_io_Cin_0 = wt28_io_Cout_0; // @[MulModule.scala 223:17]
  assign wt29_io_Cin_1 = wt28_io_Cout_1; // @[MulModule.scala 223:17]
  assign wt29_io_Cin_2 = wt28_io_Cout_2; // @[MulModule.scala 223:17]
  assign wt29_io_Cin_3 = wt28_io_Cout_3; // @[MulModule.scala 223:17]
  assign wt29_io_Cin_4 = wt28_io_Cout_4; // @[MulModule.scala 223:17]
  assign wt29_io_Cin_5 = wt28_io_Cout_5; // @[MulModule.scala 223:17]
  assign wt29_io_Cin_6 = wt28_io_Cout_6; // @[MulModule.scala 223:17]
  assign wt29_io_Cin_7 = wt28_io_Cout_7; // @[MulModule.scala 223:17]
  assign wt29_io_Cin_8 = wt28_io_Cout_8; // @[MulModule.scala 223:17]
  assign wt29_io_Cin_9 = wt28_io_Cout_9; // @[MulModule.scala 223:17]
  assign wt29_io_Cin_10 = wt28_io_Cout_10; // @[MulModule.scala 223:17]
  assign wt29_io_Cin_11 = wt28_io_Cout_11; // @[MulModule.scala 223:17]
  assign wt29_io_Cin_12 = wt28_io_Cout_12; // @[MulModule.scala 223:17]
  assign wt29_io_Cin_13 = wt28_io_Cout_13; // @[MulModule.scala 223:17]
  assign wt29_io_Cin_14 = wt28_io_Cout_14; // @[MulModule.scala 223:17]
  assign wt30_io_N = {wt30_io_N_hi,wt30_io_N_lo}; // @[Cat.scala 30:58]
  assign wt30_io_Cin_0 = wt29_io_Cout_0; // @[MulModule.scala 225:17]
  assign wt30_io_Cin_1 = wt29_io_Cout_1; // @[MulModule.scala 225:17]
  assign wt30_io_Cin_2 = wt29_io_Cout_2; // @[MulModule.scala 225:17]
  assign wt30_io_Cin_3 = wt29_io_Cout_3; // @[MulModule.scala 225:17]
  assign wt30_io_Cin_4 = wt29_io_Cout_4; // @[MulModule.scala 225:17]
  assign wt30_io_Cin_5 = wt29_io_Cout_5; // @[MulModule.scala 225:17]
  assign wt30_io_Cin_6 = wt29_io_Cout_6; // @[MulModule.scala 225:17]
  assign wt30_io_Cin_7 = wt29_io_Cout_7; // @[MulModule.scala 225:17]
  assign wt30_io_Cin_8 = wt29_io_Cout_8; // @[MulModule.scala 225:17]
  assign wt30_io_Cin_9 = wt29_io_Cout_9; // @[MulModule.scala 225:17]
  assign wt30_io_Cin_10 = wt29_io_Cout_10; // @[MulModule.scala 225:17]
  assign wt30_io_Cin_11 = wt29_io_Cout_11; // @[MulModule.scala 225:17]
  assign wt30_io_Cin_12 = wt29_io_Cout_12; // @[MulModule.scala 225:17]
  assign wt30_io_Cin_13 = wt29_io_Cout_13; // @[MulModule.scala 225:17]
  assign wt30_io_Cin_14 = wt29_io_Cout_14; // @[MulModule.scala 225:17]
  assign wt31_io_N = {wt31_io_N_hi,wt31_io_N_lo}; // @[Cat.scala 30:58]
  assign wt31_io_Cin_0 = wt30_io_Cout_0; // @[MulModule.scala 227:17]
  assign wt31_io_Cin_1 = wt30_io_Cout_1; // @[MulModule.scala 227:17]
  assign wt31_io_Cin_2 = wt30_io_Cout_2; // @[MulModule.scala 227:17]
  assign wt31_io_Cin_3 = wt30_io_Cout_3; // @[MulModule.scala 227:17]
  assign wt31_io_Cin_4 = wt30_io_Cout_4; // @[MulModule.scala 227:17]
  assign wt31_io_Cin_5 = wt30_io_Cout_5; // @[MulModule.scala 227:17]
  assign wt31_io_Cin_6 = wt30_io_Cout_6; // @[MulModule.scala 227:17]
  assign wt31_io_Cin_7 = wt30_io_Cout_7; // @[MulModule.scala 227:17]
  assign wt31_io_Cin_8 = wt30_io_Cout_8; // @[MulModule.scala 227:17]
  assign wt31_io_Cin_9 = wt30_io_Cout_9; // @[MulModule.scala 227:17]
  assign wt31_io_Cin_10 = wt30_io_Cout_10; // @[MulModule.scala 227:17]
  assign wt31_io_Cin_11 = wt30_io_Cout_11; // @[MulModule.scala 227:17]
  assign wt31_io_Cin_12 = wt30_io_Cout_12; // @[MulModule.scala 227:17]
  assign wt31_io_Cin_13 = wt30_io_Cout_13; // @[MulModule.scala 227:17]
  assign wt31_io_Cin_14 = wt30_io_Cout_14; // @[MulModule.scala 227:17]
  always @(posedge clock) begin
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_0 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_0 <= Ps_0; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_1 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_1 <= Ps_1; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_2 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_2 <= Ps_2; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_3 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_3 <= Ps_3; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_4 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_4 <= Ps_4; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_5 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_5 <= Ps_5; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_6 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_6 <= Ps_6; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_7 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_7 <= Ps_7; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_8 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_8 <= Ps_8; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_9 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_9 <= Ps_9; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_10 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_10 <= Ps_10; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_11 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_11 <= Ps_11; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_12 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_12 <= Ps_12; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_13 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_13 <= Ps_13; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_14 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_14 <= Ps_14; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 103:24]
      PsReg_15 <= 32'h0; // @[MulModule.scala 103:24]
    end else begin
      PsReg_15 <= Ps_15; // @[MulModule.scala 105:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_0 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_0 <= cs_0; // @[MulModule.scala 106:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_1 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_1 <= cs_1; // @[MulModule.scala 106:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_2 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_2 <= cs_2; // @[MulModule.scala 106:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_3 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_3 <= cs_3; // @[MulModule.scala 106:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_4 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_4 <= cs_4; // @[MulModule.scala 106:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_5 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_5 <= cs_5; // @[MulModule.scala 106:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_6 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_6 <= cs_6; // @[MulModule.scala 106:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_7 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_7 <= cs_7; // @[MulModule.scala 106:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_8 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_8 <= cs_8; // @[MulModule.scala 106:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_9 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_9 <= cs_9; // @[MulModule.scala 106:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_10 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_10 <= cs_10; // @[MulModule.scala 106:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_11 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_11 <= cs_11; // @[MulModule.scala 106:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_12 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_12 <= cs_12; // @[MulModule.scala 106:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_13 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_13 <= cs_13; // @[MulModule.scala 106:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_14 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_14 <= cs_14; // @[MulModule.scala 106:11]
    end
    if (reset) begin // @[MulModule.scala 104:24]
      csReg_15 <= 1'h0; // @[MulModule.scala 104:24]
    end else begin
      csReg_15 <= cs_15; // @[MulModule.scala 106:11]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  PsReg_0 = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  PsReg_1 = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  PsReg_2 = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  PsReg_3 = _RAND_3[31:0];
  _RAND_4 = {1{`RANDOM}};
  PsReg_4 = _RAND_4[31:0];
  _RAND_5 = {1{`RANDOM}};
  PsReg_5 = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  PsReg_6 = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  PsReg_7 = _RAND_7[31:0];
  _RAND_8 = {1{`RANDOM}};
  PsReg_8 = _RAND_8[31:0];
  _RAND_9 = {1{`RANDOM}};
  PsReg_9 = _RAND_9[31:0];
  _RAND_10 = {1{`RANDOM}};
  PsReg_10 = _RAND_10[31:0];
  _RAND_11 = {1{`RANDOM}};
  PsReg_11 = _RAND_11[31:0];
  _RAND_12 = {1{`RANDOM}};
  PsReg_12 = _RAND_12[31:0];
  _RAND_13 = {1{`RANDOM}};
  PsReg_13 = _RAND_13[31:0];
  _RAND_14 = {1{`RANDOM}};
  PsReg_14 = _RAND_14[31:0];
  _RAND_15 = {1{`RANDOM}};
  PsReg_15 = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  csReg_0 = _RAND_16[0:0];
  _RAND_17 = {1{`RANDOM}};
  csReg_1 = _RAND_17[0:0];
  _RAND_18 = {1{`RANDOM}};
  csReg_2 = _RAND_18[0:0];
  _RAND_19 = {1{`RANDOM}};
  csReg_3 = _RAND_19[0:0];
  _RAND_20 = {1{`RANDOM}};
  csReg_4 = _RAND_20[0:0];
  _RAND_21 = {1{`RANDOM}};
  csReg_5 = _RAND_21[0:0];
  _RAND_22 = {1{`RANDOM}};
  csReg_6 = _RAND_22[0:0];
  _RAND_23 = {1{`RANDOM}};
  csReg_7 = _RAND_23[0:0];
  _RAND_24 = {1{`RANDOM}};
  csReg_8 = _RAND_24[0:0];
  _RAND_25 = {1{`RANDOM}};
  csReg_9 = _RAND_25[0:0];
  _RAND_26 = {1{`RANDOM}};
  csReg_10 = _RAND_26[0:0];
  _RAND_27 = {1{`RANDOM}};
  csReg_11 = _RAND_27[0:0];
  _RAND_28 = {1{`RANDOM}};
  csReg_12 = _RAND_28[0:0];
  _RAND_29 = {1{`RANDOM}};
  csReg_13 = _RAND_29[0:0];
  _RAND_30 = {1{`RANDOM}};
  csReg_14 = _RAND_30[0:0];
  _RAND_31 = {1{`RANDOM}};
  csReg_15 = _RAND_31[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module MEMReg(
  input         clock,
  input         reset,
  input  [2:0]  io_memInfo_in_memType,
  input  [31:0] io_memInfo_in_memAddr,
  output [2:0]  io_memInfo_out_memType,
  output [31:0] io_memInfo_out_memAddr,
  input         io_wbInfo_in_regwe,
  input  [4:0]  io_wbInfo_in_regAddr,
  input  [31:0] io_wbInfo_in_wData,
  output        io_wbInfo_out_regwe,
  output [4:0]  io_wbInfo_out_regAddr,
  output [31:0] io_wbInfo_out_wData,
  input         io_valid_in
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
`endif // RANDOMIZE_REG_INIT
  reg [2:0] memType; // @[MEMReg.scala 16:26]
  reg [31:0] memAddr; // @[MEMReg.scala 17:26]
  reg  regwe; // @[MEMReg.scala 19:24]
  reg [4:0] regAddr; // @[MEMReg.scala 20:26]
  reg [31:0] wData; // @[MEMReg.scala 21:24]
  wire  _GEN_2 = io_valid_in & io_wbInfo_in_regwe; // @[MEMReg.scala 23:22 MEMReg.scala 26:15 MEMReg.scala 32:15]
  assign io_memInfo_out_memType = memType; // @[MEMReg.scala 39:28]
  assign io_memInfo_out_memAddr = memAddr; // @[MEMReg.scala 38:28]
  assign io_wbInfo_out_regwe = regwe; // @[MEMReg.scala 41:25]
  assign io_wbInfo_out_regAddr = regAddr; // @[MEMReg.scala 40:27]
  assign io_wbInfo_out_wData = wData; // @[MEMReg.scala 42:25]
  always @(posedge clock) begin
    if (reset) begin // @[MEMReg.scala 16:26]
      memType <= 3'h4; // @[MEMReg.scala 16:26]
    end else if (io_valid_in) begin // @[MEMReg.scala 23:22]
      memType <= io_memInfo_in_memType; // @[MEMReg.scala 24:17]
    end else begin
      memType <= 3'h4; // @[MEMReg.scala 30:17]
    end
    if (reset) begin // @[MEMReg.scala 17:26]
      memAddr <= 32'h0; // @[MEMReg.scala 17:26]
    end else if (io_valid_in) begin // @[MEMReg.scala 23:22]
      memAddr <= io_memInfo_in_memAddr; // @[MEMReg.scala 25:17]
    end else begin
      memAddr <= 32'h80400000; // @[MEMReg.scala 31:17]
    end
    if (reset) begin // @[MEMReg.scala 19:24]
      regwe <= 1'h0; // @[MEMReg.scala 19:24]
    end else begin
      regwe <= _GEN_2;
    end
    if (reset) begin // @[MEMReg.scala 20:26]
      regAddr <= 5'h0; // @[MEMReg.scala 20:26]
    end else if (io_valid_in) begin // @[MEMReg.scala 23:22]
      regAddr <= io_wbInfo_in_regAddr; // @[MEMReg.scala 27:17]
    end else begin
      regAddr <= 5'h0; // @[MEMReg.scala 33:17]
    end
    if (reset) begin // @[MEMReg.scala 21:24]
      wData <= 32'h0; // @[MEMReg.scala 21:24]
    end else if (io_valid_in) begin // @[MEMReg.scala 23:22]
      wData <= io_wbInfo_in_wData; // @[MEMReg.scala 28:15]
    end else begin
      wData <= 32'h0; // @[MEMReg.scala 34:15]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  memType = _RAND_0[2:0];
  _RAND_1 = {1{`RANDOM}};
  memAddr = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  regwe = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  regAddr = _RAND_3[4:0];
  _RAND_4 = {1{`RANDOM}};
  wData = _RAND_4[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module MemAccess(
  input  [2:0]  io_memInfo_memType,
  input  [31:0] io_memInfo_memAddr,
  input         io_wbInfo_in_regwe,
  input  [4:0]  io_wbInfo_in_regAddr,
  input  [31:0] io_wbInfo_in_wData,
  output        io_wbInfo_out_regwe,
  output [4:0]  io_wbInfo_out_regAddr,
  output [31:0] io_wbInfo_out_wData,
  input  [31:0] io_rdata,
  output [4:0]  io_bypassFromMem1_regAddr,
  output [31:0] io_bypassFromMem1_regData,
  output [4:0]  io_bypassFromMem2_regAddr,
  output [31:0] io_bypassFromMem2_regData,
  output        io_stallFromMEM
);
  wire  _T = io_memInfo_memType == 3'h0; // @[MemAccess.scala 27:29]
  wire  _T_1 = io_memInfo_memType == 3'h1; // @[MemAccess.scala 27:61]
  wire [4:0] _GEN_0 = io_wbInfo_in_regwe ? io_wbInfo_in_regAddr : 5'h0; // @[MemAccess.scala 36:33 MemAccess.scala 38:39 MemAccess.scala 43:39]
  wire [31:0] _GEN_1 = io_wbInfo_in_regwe ? io_wbInfo_in_wData : 32'h0; // @[MemAccess.scala 36:33 MemAccess.scala 39:39 MemAccess.scala 44:39]
  wire  _T_11 = ~io_memInfo_memAddr[22]; // @[MemAccess.scala 50:37]
  assign io_wbInfo_out_regwe = io_wbInfo_in_regwe; // @[MemAccess.scala 26:25]
  assign io_wbInfo_out_regAddr = io_wbInfo_in_regAddr; // @[MemAccess.scala 25:27]
  assign io_wbInfo_out_wData = io_memInfo_memType == 3'h0 | io_memInfo_memType == 3'h1 ? io_rdata : io_wbInfo_in_wData; // @[MemAccess.scala 27:72 MemAccess.scala 28:29 MemAccess.scala 35:29]
  assign io_bypassFromMem1_regAddr = io_memInfo_memType == 3'h0 | io_memInfo_memType == 3'h1 ? io_wbInfo_in_regAddr :
    _GEN_0; // @[MemAccess.scala 27:72 MemAccess.scala 29:35]
  assign io_bypassFromMem1_regData = io_memInfo_memType == 3'h0 | io_memInfo_memType == 3'h1 ? io_rdata : _GEN_1; // @[MemAccess.scala 27:72 MemAccess.scala 30:35]
  assign io_bypassFromMem2_regAddr = io_memInfo_memType == 3'h0 | io_memInfo_memType == 3'h1 ? io_wbInfo_in_regAddr :
    _GEN_0; // @[MemAccess.scala 27:72 MemAccess.scala 29:35]
  assign io_bypassFromMem2_regData = io_memInfo_memType == 3'h0 | io_memInfo_memType == 3'h1 ? io_rdata : _GEN_1; // @[MemAccess.scala 27:72 MemAccess.scala 30:35]
  assign io_stallFromMEM = (io_memInfo_memType == 3'h2 | io_memInfo_memType == 3'h3 | _T | _T_1) & _T_11; // @[MemAccess.scala 49:135 MemAccess.scala 56:25]
endmodule
module WBReg(
  input         clock,
  input         reset,
  input         io_wbInfo_regwe,
  input  [4:0]  io_wbInfo_regAddr,
  input  [31:0] io_wbInfo_wData,
  output        io_write_we,
  output [4:0]  io_write_addr,
  output [31:0] io_write_wdata
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  reg  we; // @[WBReg.scala 13:21]
  reg [4:0] addr; // @[WBReg.scala 14:23]
  reg [31:0] wdata; // @[WBReg.scala 15:24]
  assign io_write_we = we; // @[WBReg.scala 23:17]
  assign io_write_addr = addr; // @[WBReg.scala 21:19]
  assign io_write_wdata = wdata; // @[WBReg.scala 22:20]
  always @(posedge clock) begin
    if (reset) begin // @[WBReg.scala 13:21]
      we <= 1'h0; // @[WBReg.scala 13:21]
    end else begin
      we <= io_wbInfo_regwe; // @[WBReg.scala 17:8]
    end
    if (reset) begin // @[WBReg.scala 14:23]
      addr <= 5'h0; // @[WBReg.scala 14:23]
    end else begin
      addr <= io_wbInfo_regAddr; // @[WBReg.scala 18:10]
    end
    if (reset) begin // @[WBReg.scala 15:24]
      wdata <= 32'h0; // @[WBReg.scala 15:24]
    end else begin
      wdata <= io_wbInfo_wData; // @[WBReg.scala 19:11]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  we = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  addr = _RAND_1[4:0];
  _RAND_2 = {1{`RANDOM}};
  wdata = _RAND_2[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module RegFile(
  input         clock,
  input         reset,
  input  [4:0]  io_read_rsAddr,
  input  [4:0]  io_read_rtAddr,
  output [31:0] io_read_rsData,
  output [31:0] io_read_rtData,
  input         io_write_we,
  input  [4:0]  io_write_addr,
  input  [31:0] io_write_wdata
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
`endif // RANDOMIZE_REG_INIT
  reg [31:0] regs_0; // @[RegFile.scala 20:23]
  reg [31:0] regs_1; // @[RegFile.scala 20:23]
  reg [31:0] regs_2; // @[RegFile.scala 20:23]
  reg [31:0] regs_3; // @[RegFile.scala 20:23]
  reg [31:0] regs_4; // @[RegFile.scala 20:23]
  reg [31:0] regs_5; // @[RegFile.scala 20:23]
  reg [31:0] regs_6; // @[RegFile.scala 20:23]
  reg [31:0] regs_7; // @[RegFile.scala 20:23]
  reg [31:0] regs_8; // @[RegFile.scala 20:23]
  reg [31:0] regs_9; // @[RegFile.scala 20:23]
  reg [31:0] regs_10; // @[RegFile.scala 20:23]
  reg [31:0] regs_11; // @[RegFile.scala 20:23]
  reg [31:0] regs_12; // @[RegFile.scala 20:23]
  reg [31:0] regs_13; // @[RegFile.scala 20:23]
  reg [31:0] regs_14; // @[RegFile.scala 20:23]
  reg [31:0] regs_15; // @[RegFile.scala 20:23]
  reg [31:0] regs_16; // @[RegFile.scala 20:23]
  reg [31:0] regs_17; // @[RegFile.scala 20:23]
  reg [31:0] regs_18; // @[RegFile.scala 20:23]
  reg [31:0] regs_19; // @[RegFile.scala 20:23]
  reg [31:0] regs_20; // @[RegFile.scala 20:23]
  reg [31:0] regs_21; // @[RegFile.scala 20:23]
  reg [31:0] regs_22; // @[RegFile.scala 20:23]
  reg [31:0] regs_23; // @[RegFile.scala 20:23]
  reg [31:0] regs_24; // @[RegFile.scala 20:23]
  reg [31:0] regs_25; // @[RegFile.scala 20:23]
  reg [31:0] regs_26; // @[RegFile.scala 20:23]
  reg [31:0] regs_27; // @[RegFile.scala 20:23]
  reg [31:0] regs_28; // @[RegFile.scala 20:23]
  reg [31:0] regs_29; // @[RegFile.scala 20:23]
  reg [31:0] regs_30; // @[RegFile.scala 20:23]
  reg [31:0] regs_31; // @[RegFile.scala 20:23]
  wire  _T = io_write_addr != 5'h0; // @[RegFile.scala 21:39]
  wire [31:0] _GEN_65 = 5'h1 == io_read_rsAddr ? regs_1 : regs_0; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_66 = 5'h2 == io_read_rsAddr ? regs_2 : _GEN_65; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_67 = 5'h3 == io_read_rsAddr ? regs_3 : _GEN_66; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_68 = 5'h4 == io_read_rsAddr ? regs_4 : _GEN_67; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_69 = 5'h5 == io_read_rsAddr ? regs_5 : _GEN_68; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_70 = 5'h6 == io_read_rsAddr ? regs_6 : _GEN_69; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_71 = 5'h7 == io_read_rsAddr ? regs_7 : _GEN_70; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_72 = 5'h8 == io_read_rsAddr ? regs_8 : _GEN_71; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_73 = 5'h9 == io_read_rsAddr ? regs_9 : _GEN_72; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_74 = 5'ha == io_read_rsAddr ? regs_10 : _GEN_73; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_75 = 5'hb == io_read_rsAddr ? regs_11 : _GEN_74; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_76 = 5'hc == io_read_rsAddr ? regs_12 : _GEN_75; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_77 = 5'hd == io_read_rsAddr ? regs_13 : _GEN_76; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_78 = 5'he == io_read_rsAddr ? regs_14 : _GEN_77; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_79 = 5'hf == io_read_rsAddr ? regs_15 : _GEN_78; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_80 = 5'h10 == io_read_rsAddr ? regs_16 : _GEN_79; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_81 = 5'h11 == io_read_rsAddr ? regs_17 : _GEN_80; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_82 = 5'h12 == io_read_rsAddr ? regs_18 : _GEN_81; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_83 = 5'h13 == io_read_rsAddr ? regs_19 : _GEN_82; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_84 = 5'h14 == io_read_rsAddr ? regs_20 : _GEN_83; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_85 = 5'h15 == io_read_rsAddr ? regs_21 : _GEN_84; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_86 = 5'h16 == io_read_rsAddr ? regs_22 : _GEN_85; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_87 = 5'h17 == io_read_rsAddr ? regs_23 : _GEN_86; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_88 = 5'h18 == io_read_rsAddr ? regs_24 : _GEN_87; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_89 = 5'h19 == io_read_rsAddr ? regs_25 : _GEN_88; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_90 = 5'h1a == io_read_rsAddr ? regs_26 : _GEN_89; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_91 = 5'h1b == io_read_rsAddr ? regs_27 : _GEN_90; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_92 = 5'h1c == io_read_rsAddr ? regs_28 : _GEN_91; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_93 = 5'h1d == io_read_rsAddr ? regs_29 : _GEN_92; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_94 = 5'h1e == io_read_rsAddr ? regs_30 : _GEN_93; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_95 = 5'h1f == io_read_rsAddr ? regs_31 : _GEN_94; // @[RegFile.scala 28:24 RegFile.scala 28:24]
  wire [31:0] _GEN_98 = 5'h1 == io_read_rtAddr ? regs_1 : regs_0; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_99 = 5'h2 == io_read_rtAddr ? regs_2 : _GEN_98; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_100 = 5'h3 == io_read_rtAddr ? regs_3 : _GEN_99; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_101 = 5'h4 == io_read_rtAddr ? regs_4 : _GEN_100; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_102 = 5'h5 == io_read_rtAddr ? regs_5 : _GEN_101; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_103 = 5'h6 == io_read_rtAddr ? regs_6 : _GEN_102; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_104 = 5'h7 == io_read_rtAddr ? regs_7 : _GEN_103; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_105 = 5'h8 == io_read_rtAddr ? regs_8 : _GEN_104; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_106 = 5'h9 == io_read_rtAddr ? regs_9 : _GEN_105; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_107 = 5'ha == io_read_rtAddr ? regs_10 : _GEN_106; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_108 = 5'hb == io_read_rtAddr ? regs_11 : _GEN_107; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_109 = 5'hc == io_read_rtAddr ? regs_12 : _GEN_108; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_110 = 5'hd == io_read_rtAddr ? regs_13 : _GEN_109; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_111 = 5'he == io_read_rtAddr ? regs_14 : _GEN_110; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_112 = 5'hf == io_read_rtAddr ? regs_15 : _GEN_111; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_113 = 5'h10 == io_read_rtAddr ? regs_16 : _GEN_112; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_114 = 5'h11 == io_read_rtAddr ? regs_17 : _GEN_113; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_115 = 5'h12 == io_read_rtAddr ? regs_18 : _GEN_114; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_116 = 5'h13 == io_read_rtAddr ? regs_19 : _GEN_115; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_117 = 5'h14 == io_read_rtAddr ? regs_20 : _GEN_116; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_118 = 5'h15 == io_read_rtAddr ? regs_21 : _GEN_117; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_119 = 5'h16 == io_read_rtAddr ? regs_22 : _GEN_118; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_120 = 5'h17 == io_read_rtAddr ? regs_23 : _GEN_119; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_121 = 5'h18 == io_read_rtAddr ? regs_24 : _GEN_120; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_122 = 5'h19 == io_read_rtAddr ? regs_25 : _GEN_121; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_123 = 5'h1a == io_read_rtAddr ? regs_26 : _GEN_122; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_124 = 5'h1b == io_read_rtAddr ? regs_27 : _GEN_123; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_125 = 5'h1c == io_read_rtAddr ? regs_28 : _GEN_124; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_126 = 5'h1d == io_read_rtAddr ? regs_29 : _GEN_125; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_127 = 5'h1e == io_read_rtAddr ? regs_30 : _GEN_126; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  wire [31:0] _GEN_128 = 5'h1f == io_read_rtAddr ? regs_31 : _GEN_127; // @[RegFile.scala 34:24 RegFile.scala 34:24]
  assign io_read_rsData = io_write_we & io_write_addr == io_read_rsAddr & _T ? io_write_wdata : _GEN_95; // @[RegFile.scala 25:84 RegFile.scala 26:24 RegFile.scala 28:24]
  assign io_read_rtData = io_write_we & io_write_addr == io_read_rtAddr & _T ? io_write_wdata : _GEN_128; // @[RegFile.scala 31:84 RegFile.scala 32:24 RegFile.scala 34:24]
  always @(posedge clock) begin
    if (reset) begin // @[RegFile.scala 20:23]
      regs_0 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h0 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_0 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_1 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h1 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_1 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_2 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h2 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_2 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_3 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h3 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_3 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_4 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h4 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_4 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_5 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h5 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_5 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_6 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h6 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_6 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_7 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h7 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_7 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_8 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h8 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_8 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_9 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h9 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_9 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_10 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'ha == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_10 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_11 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'hb == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_11 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_12 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'hc == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_12 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_13 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'hd == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_13 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_14 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'he == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_14 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_15 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'hf == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_15 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_16 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h10 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_16 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_17 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h11 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_17 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_18 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h12 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_18 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_19 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h13 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_19 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_20 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h14 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_20 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_21 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h15 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_21 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_22 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h16 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_22 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_23 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h17 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_23 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_24 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h18 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_24 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_25 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h19 == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_25 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_26 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h1a == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_26 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_27 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h1b == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_27 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_28 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h1c == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_28 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_29 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h1d == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_29 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_30 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h1e == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_30 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
    if (reset) begin // @[RegFile.scala 20:23]
      regs_31 <= 32'h0; // @[RegFile.scala 20:23]
    end else if (io_write_we & io_write_addr != 5'h0) begin // @[RegFile.scala 21:48]
      if (5'h1f == io_write_addr) begin // @[RegFile.scala 22:29]
        regs_31 <= io_write_wdata; // @[RegFile.scala 22:29]
      end
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  regs_0 = _RAND_0[31:0];
  _RAND_1 = {1{`RANDOM}};
  regs_1 = _RAND_1[31:0];
  _RAND_2 = {1{`RANDOM}};
  regs_2 = _RAND_2[31:0];
  _RAND_3 = {1{`RANDOM}};
  regs_3 = _RAND_3[31:0];
  _RAND_4 = {1{`RANDOM}};
  regs_4 = _RAND_4[31:0];
  _RAND_5 = {1{`RANDOM}};
  regs_5 = _RAND_5[31:0];
  _RAND_6 = {1{`RANDOM}};
  regs_6 = _RAND_6[31:0];
  _RAND_7 = {1{`RANDOM}};
  regs_7 = _RAND_7[31:0];
  _RAND_8 = {1{`RANDOM}};
  regs_8 = _RAND_8[31:0];
  _RAND_9 = {1{`RANDOM}};
  regs_9 = _RAND_9[31:0];
  _RAND_10 = {1{`RANDOM}};
  regs_10 = _RAND_10[31:0];
  _RAND_11 = {1{`RANDOM}};
  regs_11 = _RAND_11[31:0];
  _RAND_12 = {1{`RANDOM}};
  regs_12 = _RAND_12[31:0];
  _RAND_13 = {1{`RANDOM}};
  regs_13 = _RAND_13[31:0];
  _RAND_14 = {1{`RANDOM}};
  regs_14 = _RAND_14[31:0];
  _RAND_15 = {1{`RANDOM}};
  regs_15 = _RAND_15[31:0];
  _RAND_16 = {1{`RANDOM}};
  regs_16 = _RAND_16[31:0];
  _RAND_17 = {1{`RANDOM}};
  regs_17 = _RAND_17[31:0];
  _RAND_18 = {1{`RANDOM}};
  regs_18 = _RAND_18[31:0];
  _RAND_19 = {1{`RANDOM}};
  regs_19 = _RAND_19[31:0];
  _RAND_20 = {1{`RANDOM}};
  regs_20 = _RAND_20[31:0];
  _RAND_21 = {1{`RANDOM}};
  regs_21 = _RAND_21[31:0];
  _RAND_22 = {1{`RANDOM}};
  regs_22 = _RAND_22[31:0];
  _RAND_23 = {1{`RANDOM}};
  regs_23 = _RAND_23[31:0];
  _RAND_24 = {1{`RANDOM}};
  regs_24 = _RAND_24[31:0];
  _RAND_25 = {1{`RANDOM}};
  regs_25 = _RAND_25[31:0];
  _RAND_26 = {1{`RANDOM}};
  regs_26 = _RAND_26[31:0];
  _RAND_27 = {1{`RANDOM}};
  regs_27 = _RAND_27[31:0];
  _RAND_28 = {1{`RANDOM}};
  regs_28 = _RAND_28[31:0];
  _RAND_29 = {1{`RANDOM}};
  regs_29 = _RAND_29[31:0];
  _RAND_30 = {1{`RANDOM}};
  regs_30 = _RAND_30[31:0];
  _RAND_31 = {1{`RANDOM}};
  regs_31 = _RAND_31[31:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module XunChunTop(
  input         clock,
  input         reset,
  input  [31:0] io_if_rdata,
  input  [31:0] io_mem_rdata,
  output [31:0] io_if_addr,
  output [31:0] io_mem_addr,
  output        io_mem_wr,
  output [1:0]  io_mem_size,
  output [31:0] io_mem_wdata
);
  wire  pc_clock; // @[XunChunTop.scala 26:20]
  wire  pc_reset; // @[XunChunTop.scala 26:20]
  wire  pc_io_ready_in; // @[XunChunTop.scala 26:20]
  wire  pc_io_valid_out; // @[XunChunTop.scala 26:20]
  wire [31:0] pc_io_npc; // @[XunChunTop.scala 26:20]
  wire [31:0] pc_io_pc; // @[XunChunTop.scala 26:20]
  wire  pc_io_NPC_Type; // @[XunChunTop.scala 26:20]
  wire [31:0] pc_io_pcImm; // @[XunChunTop.scala 26:20]
  wire  pc_io_stall; // @[XunChunTop.scala 26:20]
  wire  idreg_clock; // @[XunChunTop.scala 28:23]
  wire  idreg_reset; // @[XunChunTop.scala 28:23]
  wire [31:0] idreg_io_pc_in; // @[XunChunTop.scala 28:23]
  wire [31:0] idreg_io_pc_out; // @[XunChunTop.scala 28:23]
  wire [31:0] idreg_io_instr_in; // @[XunChunTop.scala 28:23]
  wire [31:0] idreg_io_instr_out; // @[XunChunTop.scala 28:23]
  wire  idreg_io_ready_in; // @[XunChunTop.scala 28:23]
  wire  idreg_io_ready_out; // @[XunChunTop.scala 28:23]
  wire  idreg_io_valid_in; // @[XunChunTop.scala 28:23]
  wire  idreg_io_valid_out; // @[XunChunTop.scala 28:23]
  wire  idreg_io_stallFromIF; // @[XunChunTop.scala 28:23]
  wire  idreg_io_stallFromEXE; // @[XunChunTop.scala 28:23]
  wire  idreg_io_stallFromMEM; // @[XunChunTop.scala 28:23]
  wire [31:0] decode_io_instr_in; // @[XunChunTop.scala 29:24]
  wire [31:0] decode_io_pc_in; // @[XunChunTop.scala 29:24]
  wire  decode_io_controlInfo_regwe; // @[XunChunTop.scala 29:24]
  wire [1:0] decode_io_controlInfo_wAddrSel; // @[XunChunTop.scala 29:24]
  wire [2:0] decode_io_controlInfo_ASel; // @[XunChunTop.scala 29:24]
  wire [2:0] decode_io_controlInfo_BSel; // @[XunChunTop.scala 29:24]
  wire [1:0] decode_io_controlInfo_immExtType; // @[XunChunTop.scala 29:24]
  wire [7:0] decode_io_controlInfo_op; // @[XunChunTop.scala 29:24]
  wire [31:0] decode_io_instr_out; // @[XunChunTop.scala 29:24]
  wire [31:0] decode_io_pc_out; // @[XunChunTop.scala 29:24]
  wire  decode_io_ready_out; // @[XunChunTop.scala 29:24]
  wire  decode_io_ready_in; // @[XunChunTop.scala 29:24]
  wire  control_io_controlInfo_regwe; // @[XunChunTop.scala 30:25]
  wire [1:0] control_io_controlInfo_wAddrSel; // @[XunChunTop.scala 30:25]
  wire [2:0] control_io_controlInfo_ASel; // @[XunChunTop.scala 30:25]
  wire [2:0] control_io_controlInfo_BSel; // @[XunChunTop.scala 30:25]
  wire [1:0] control_io_controlInfo_immExtType; // @[XunChunTop.scala 30:25]
  wire [7:0] control_io_controlInfo_op; // @[XunChunTop.scala 30:25]
  wire [31:0] control_io_instr; // @[XunChunTop.scala 30:25]
  wire [31:0] control_io_pc; // @[XunChunTop.scala 30:25]
  wire [31:0] control_io_rsData; // @[XunChunTop.scala 30:25]
  wire [31:0] control_io_rtData; // @[XunChunTop.scala 30:25]
  wire [4:0] control_io_bypassFromExe_regAddr; // @[XunChunTop.scala 30:25]
  wire [31:0] control_io_bypassFromExe_regData; // @[XunChunTop.scala 30:25]
  wire [4:0] control_io_bypassFromMem_regAddr; // @[XunChunTop.scala 30:25]
  wire [31:0] control_io_bypassFromMem_regData; // @[XunChunTop.scala 30:25]
  wire [4:0] control_io_rsAddr; // @[XunChunTop.scala 30:25]
  wire [4:0] control_io_rtAddr; // @[XunChunTop.scala 30:25]
  wire  control_io_NPC_Type; // @[XunChunTop.scala 30:25]
  wire [31:0] control_io_NextPC; // @[XunChunTop.scala 30:25]
  wire [31:0] control_io_exeInfo_OperA; // @[XunChunTop.scala 30:25]
  wire [31:0] control_io_exeInfo_OperB; // @[XunChunTop.scala 30:25]
  wire  control_io_exeInfo_regwe; // @[XunChunTop.scala 30:25]
  wire [4:0] control_io_exeInfo_wAddr; // @[XunChunTop.scala 30:25]
  wire [7:0] control_io_exeInfo_op; // @[XunChunTop.scala 30:25]
  wire  control_io_exeInfo_AFromReg; // @[XunChunTop.scala 30:25]
  wire  control_io_exeInfo_BFromReg; // @[XunChunTop.scala 30:25]
  wire [4:0] control_io_exeInfo_ARegAddr; // @[XunChunTop.scala 30:25]
  wire [4:0] control_io_exeInfo_BRegAddr; // @[XunChunTop.scala 30:25]
  wire  control_io_ready_in; // @[XunChunTop.scala 30:25]
  wire  control_io_ready_out; // @[XunChunTop.scala 30:25]
  wire  control_io_valid_in; // @[XunChunTop.scala 30:25]
  wire  control_io_valid_out; // @[XunChunTop.scala 30:25]
  wire  control_io_isLBandLW; // @[XunChunTop.scala 30:25]
  wire [4:0] control_io_wregAddr; // @[XunChunTop.scala 30:25]
  wire  control_io_stallFromID; // @[XunChunTop.scala 30:25]
  wire  exereg_clock; // @[XunChunTop.scala 32:24]
  wire  exereg_reset; // @[XunChunTop.scala 32:24]
  wire [31:0] exereg_io_exeInfo_in_OperA; // @[XunChunTop.scala 32:24]
  wire [31:0] exereg_io_exeInfo_in_OperB; // @[XunChunTop.scala 32:24]
  wire  exereg_io_exeInfo_in_regwe; // @[XunChunTop.scala 32:24]
  wire [4:0] exereg_io_exeInfo_in_wAddr; // @[XunChunTop.scala 32:24]
  wire [7:0] exereg_io_exeInfo_in_op; // @[XunChunTop.scala 32:24]
  wire  exereg_io_exeInfo_in_AFromReg; // @[XunChunTop.scala 32:24]
  wire  exereg_io_exeInfo_in_BFromReg; // @[XunChunTop.scala 32:24]
  wire [4:0] exereg_io_exeInfo_in_ARegAddr; // @[XunChunTop.scala 32:24]
  wire [4:0] exereg_io_exeInfo_in_BRegAddr; // @[XunChunTop.scala 32:24]
  wire [31:0] exereg_io_exeInfo_out_OperA; // @[XunChunTop.scala 32:24]
  wire [31:0] exereg_io_exeInfo_out_OperB; // @[XunChunTop.scala 32:24]
  wire  exereg_io_exeInfo_out_regwe; // @[XunChunTop.scala 32:24]
  wire [4:0] exereg_io_exeInfo_out_wAddr; // @[XunChunTop.scala 32:24]
  wire [7:0] exereg_io_exeInfo_out_op; // @[XunChunTop.scala 32:24]
  wire  exereg_io_exeInfo_out_AFromReg; // @[XunChunTop.scala 32:24]
  wire  exereg_io_exeInfo_out_BFromReg; // @[XunChunTop.scala 32:24]
  wire [4:0] exereg_io_exeInfo_out_ARegAddr; // @[XunChunTop.scala 32:24]
  wire [4:0] exereg_io_exeInfo_out_BRegAddr; // @[XunChunTop.scala 32:24]
  wire  exereg_io_valid_in; // @[XunChunTop.scala 32:24]
  wire  exereg_io_ready_in; // @[XunChunTop.scala 32:24]
  wire  exereg_io_ready_out; // @[XunChunTop.scala 32:24]
  wire  alu_clock; // @[XunChunTop.scala 33:21]
  wire  alu_reset; // @[XunChunTop.scala 33:21]
  wire  alu_io_ready_out; // @[XunChunTop.scala 33:21]
  wire  alu_io_valid_out; // @[XunChunTop.scala 33:21]
  wire [31:0] alu_io_exeInfo_OperA; // @[XunChunTop.scala 33:21]
  wire [31:0] alu_io_exeInfo_OperB; // @[XunChunTop.scala 33:21]
  wire  alu_io_exeInfo_regwe; // @[XunChunTop.scala 33:21]
  wire [4:0] alu_io_exeInfo_wAddr; // @[XunChunTop.scala 33:21]
  wire [7:0] alu_io_exeInfo_op; // @[XunChunTop.scala 33:21]
  wire  alu_io_exeInfo_AFromReg; // @[XunChunTop.scala 33:21]
  wire  alu_io_exeInfo_BFromReg; // @[XunChunTop.scala 33:21]
  wire [4:0] alu_io_exeInfo_ARegAddr; // @[XunChunTop.scala 33:21]
  wire [4:0] alu_io_exeInfo_BRegAddr; // @[XunChunTop.scala 33:21]
  wire [2:0] alu_io_memInfo_memType; // @[XunChunTop.scala 33:21]
  wire [31:0] alu_io_memInfo_memAddr; // @[XunChunTop.scala 33:21]
  wire  alu_io_wbInfo_regwe; // @[XunChunTop.scala 33:21]
  wire [4:0] alu_io_wbInfo_regAddr; // @[XunChunTop.scala 33:21]
  wire [31:0] alu_io_wbInfo_wData; // @[XunChunTop.scala 33:21]
  wire [4:0] alu_io_bypassFromExe_regAddr; // @[XunChunTop.scala 33:21]
  wire [31:0] alu_io_bypassFromExe_regData; // @[XunChunTop.scala 33:21]
  wire [4:0] alu_io_bypassFromMem2_regAddr; // @[XunChunTop.scala 33:21]
  wire [31:0] alu_io_bypassFromMem2_regData; // @[XunChunTop.scala 33:21]
  wire  alu_io_isLBandLW; // @[XunChunTop.scala 33:21]
  wire [4:0] alu_io_wregAddr; // @[XunChunTop.scala 33:21]
  wire  alu_io_stallFromEXE; // @[XunChunTop.scala 33:21]
  wire [31:0] alu_io_addr; // @[XunChunTop.scala 33:21]
  wire  alu_io_wr; // @[XunChunTop.scala 33:21]
  wire [1:0] alu_io_size; // @[XunChunTop.scala 33:21]
  wire [31:0] alu_io_wdata; // @[XunChunTop.scala 33:21]
  wire [31:0] alu_io_OpA; // @[XunChunTop.scala 33:21]
  wire [31:0] alu_io_OpB; // @[XunChunTop.scala 33:21]
  wire [31:0] alu_io_mulans; // @[XunChunTop.scala 33:21]
  wire  mulmodule_clock; // @[XunChunTop.scala 34:27]
  wire  mulmodule_reset; // @[XunChunTop.scala 34:27]
  wire [31:0] mulmodule_io_OpA; // @[XunChunTop.scala 34:27]
  wire [31:0] mulmodule_io_OpB; // @[XunChunTop.scala 34:27]
  wire [31:0] mulmodule_io_ans; // @[XunChunTop.scala 34:27]
  wire  memreg_clock; // @[XunChunTop.scala 36:24]
  wire  memreg_reset; // @[XunChunTop.scala 36:24]
  wire [2:0] memreg_io_memInfo_in_memType; // @[XunChunTop.scala 36:24]
  wire [31:0] memreg_io_memInfo_in_memAddr; // @[XunChunTop.scala 36:24]
  wire [2:0] memreg_io_memInfo_out_memType; // @[XunChunTop.scala 36:24]
  wire [31:0] memreg_io_memInfo_out_memAddr; // @[XunChunTop.scala 36:24]
  wire  memreg_io_wbInfo_in_regwe; // @[XunChunTop.scala 36:24]
  wire [4:0] memreg_io_wbInfo_in_regAddr; // @[XunChunTop.scala 36:24]
  wire [31:0] memreg_io_wbInfo_in_wData; // @[XunChunTop.scala 36:24]
  wire  memreg_io_wbInfo_out_regwe; // @[XunChunTop.scala 36:24]
  wire [4:0] memreg_io_wbInfo_out_regAddr; // @[XunChunTop.scala 36:24]
  wire [31:0] memreg_io_wbInfo_out_wData; // @[XunChunTop.scala 36:24]
  wire  memreg_io_valid_in; // @[XunChunTop.scala 36:24]
  wire [2:0] memaccess_io_memInfo_memType; // @[XunChunTop.scala 37:27]
  wire [31:0] memaccess_io_memInfo_memAddr; // @[XunChunTop.scala 37:27]
  wire  memaccess_io_wbInfo_in_regwe; // @[XunChunTop.scala 37:27]
  wire [4:0] memaccess_io_wbInfo_in_regAddr; // @[XunChunTop.scala 37:27]
  wire [31:0] memaccess_io_wbInfo_in_wData; // @[XunChunTop.scala 37:27]
  wire  memaccess_io_wbInfo_out_regwe; // @[XunChunTop.scala 37:27]
  wire [4:0] memaccess_io_wbInfo_out_regAddr; // @[XunChunTop.scala 37:27]
  wire [31:0] memaccess_io_wbInfo_out_wData; // @[XunChunTop.scala 37:27]
  wire [31:0] memaccess_io_rdata; // @[XunChunTop.scala 37:27]
  wire [4:0] memaccess_io_bypassFromMem1_regAddr; // @[XunChunTop.scala 37:27]
  wire [31:0] memaccess_io_bypassFromMem1_regData; // @[XunChunTop.scala 37:27]
  wire [4:0] memaccess_io_bypassFromMem2_regAddr; // @[XunChunTop.scala 37:27]
  wire [31:0] memaccess_io_bypassFromMem2_regData; // @[XunChunTop.scala 37:27]
  wire  memaccess_io_stallFromMEM; // @[XunChunTop.scala 37:27]
  wire  wbreg_clock; // @[XunChunTop.scala 39:23]
  wire  wbreg_reset; // @[XunChunTop.scala 39:23]
  wire  wbreg_io_wbInfo_regwe; // @[XunChunTop.scala 39:23]
  wire [4:0] wbreg_io_wbInfo_regAddr; // @[XunChunTop.scala 39:23]
  wire [31:0] wbreg_io_wbInfo_wData; // @[XunChunTop.scala 39:23]
  wire  wbreg_io_write_we; // @[XunChunTop.scala 39:23]
  wire [4:0] wbreg_io_write_addr; // @[XunChunTop.scala 39:23]
  wire [31:0] wbreg_io_write_wdata; // @[XunChunTop.scala 39:23]
  wire  regfile_clock; // @[XunChunTop.scala 41:25]
  wire  regfile_reset; // @[XunChunTop.scala 41:25]
  wire [4:0] regfile_io_read_rsAddr; // @[XunChunTop.scala 41:25]
  wire [4:0] regfile_io_read_rtAddr; // @[XunChunTop.scala 41:25]
  wire [31:0] regfile_io_read_rsData; // @[XunChunTop.scala 41:25]
  wire [31:0] regfile_io_read_rtData; // @[XunChunTop.scala 41:25]
  wire  regfile_io_write_we; // @[XunChunTop.scala 41:25]
  wire [4:0] regfile_io_write_addr; // @[XunChunTop.scala 41:25]
  wire [31:0] regfile_io_write_wdata; // @[XunChunTop.scala 41:25]
  PC pc ( // @[XunChunTop.scala 26:20]
    .clock(pc_clock),
    .reset(pc_reset),
    .io_ready_in(pc_io_ready_in),
    .io_valid_out(pc_io_valid_out),
    .io_npc(pc_io_npc),
    .io_pc(pc_io_pc),
    .io_NPC_Type(pc_io_NPC_Type),
    .io_pcImm(pc_io_pcImm),
    .io_stall(pc_io_stall)
  );
  IDReg idreg ( // @[XunChunTop.scala 28:23]
    .clock(idreg_clock),
    .reset(idreg_reset),
    .io_pc_in(idreg_io_pc_in),
    .io_pc_out(idreg_io_pc_out),
    .io_instr_in(idreg_io_instr_in),
    .io_instr_out(idreg_io_instr_out),
    .io_ready_in(idreg_io_ready_in),
    .io_ready_out(idreg_io_ready_out),
    .io_valid_in(idreg_io_valid_in),
    .io_valid_out(idreg_io_valid_out),
    .io_stallFromIF(idreg_io_stallFromIF),
    .io_stallFromEXE(idreg_io_stallFromEXE),
    .io_stallFromMEM(idreg_io_stallFromMEM)
  );
  Decode decode ( // @[XunChunTop.scala 29:24]
    .io_instr_in(decode_io_instr_in),
    .io_pc_in(decode_io_pc_in),
    .io_controlInfo_regwe(decode_io_controlInfo_regwe),
    .io_controlInfo_wAddrSel(decode_io_controlInfo_wAddrSel),
    .io_controlInfo_ASel(decode_io_controlInfo_ASel),
    .io_controlInfo_BSel(decode_io_controlInfo_BSel),
    .io_controlInfo_immExtType(decode_io_controlInfo_immExtType),
    .io_controlInfo_op(decode_io_controlInfo_op),
    .io_instr_out(decode_io_instr_out),
    .io_pc_out(decode_io_pc_out),
    .io_ready_out(decode_io_ready_out),
    .io_ready_in(decode_io_ready_in)
  );
  Control control ( // @[XunChunTop.scala 30:25]
    .io_controlInfo_regwe(control_io_controlInfo_regwe),
    .io_controlInfo_wAddrSel(control_io_controlInfo_wAddrSel),
    .io_controlInfo_ASel(control_io_controlInfo_ASel),
    .io_controlInfo_BSel(control_io_controlInfo_BSel),
    .io_controlInfo_immExtType(control_io_controlInfo_immExtType),
    .io_controlInfo_op(control_io_controlInfo_op),
    .io_instr(control_io_instr),
    .io_pc(control_io_pc),
    .io_rsData(control_io_rsData),
    .io_rtData(control_io_rtData),
    .io_bypassFromExe_regAddr(control_io_bypassFromExe_regAddr),
    .io_bypassFromExe_regData(control_io_bypassFromExe_regData),
    .io_bypassFromMem_regAddr(control_io_bypassFromMem_regAddr),
    .io_bypassFromMem_regData(control_io_bypassFromMem_regData),
    .io_rsAddr(control_io_rsAddr),
    .io_rtAddr(control_io_rtAddr),
    .io_NPC_Type(control_io_NPC_Type),
    .io_NextPC(control_io_NextPC),
    .io_exeInfo_OperA(control_io_exeInfo_OperA),
    .io_exeInfo_OperB(control_io_exeInfo_OperB),
    .io_exeInfo_regwe(control_io_exeInfo_regwe),
    .io_exeInfo_wAddr(control_io_exeInfo_wAddr),
    .io_exeInfo_op(control_io_exeInfo_op),
    .io_exeInfo_AFromReg(control_io_exeInfo_AFromReg),
    .io_exeInfo_BFromReg(control_io_exeInfo_BFromReg),
    .io_exeInfo_ARegAddr(control_io_exeInfo_ARegAddr),
    .io_exeInfo_BRegAddr(control_io_exeInfo_BRegAddr),
    .io_ready_in(control_io_ready_in),
    .io_ready_out(control_io_ready_out),
    .io_valid_in(control_io_valid_in),
    .io_valid_out(control_io_valid_out),
    .io_isLBandLW(control_io_isLBandLW),
    .io_wregAddr(control_io_wregAddr),
    .io_stallFromID(control_io_stallFromID)
  );
  EXEReg exereg ( // @[XunChunTop.scala 32:24]
    .clock(exereg_clock),
    .reset(exereg_reset),
    .io_exeInfo_in_OperA(exereg_io_exeInfo_in_OperA),
    .io_exeInfo_in_OperB(exereg_io_exeInfo_in_OperB),
    .io_exeInfo_in_regwe(exereg_io_exeInfo_in_regwe),
    .io_exeInfo_in_wAddr(exereg_io_exeInfo_in_wAddr),
    .io_exeInfo_in_op(exereg_io_exeInfo_in_op),
    .io_exeInfo_in_AFromReg(exereg_io_exeInfo_in_AFromReg),
    .io_exeInfo_in_BFromReg(exereg_io_exeInfo_in_BFromReg),
    .io_exeInfo_in_ARegAddr(exereg_io_exeInfo_in_ARegAddr),
    .io_exeInfo_in_BRegAddr(exereg_io_exeInfo_in_BRegAddr),
    .io_exeInfo_out_OperA(exereg_io_exeInfo_out_OperA),
    .io_exeInfo_out_OperB(exereg_io_exeInfo_out_OperB),
    .io_exeInfo_out_regwe(exereg_io_exeInfo_out_regwe),
    .io_exeInfo_out_wAddr(exereg_io_exeInfo_out_wAddr),
    .io_exeInfo_out_op(exereg_io_exeInfo_out_op),
    .io_exeInfo_out_AFromReg(exereg_io_exeInfo_out_AFromReg),
    .io_exeInfo_out_BFromReg(exereg_io_exeInfo_out_BFromReg),
    .io_exeInfo_out_ARegAddr(exereg_io_exeInfo_out_ARegAddr),
    .io_exeInfo_out_BRegAddr(exereg_io_exeInfo_out_BRegAddr),
    .io_valid_in(exereg_io_valid_in),
    .io_ready_in(exereg_io_ready_in),
    .io_ready_out(exereg_io_ready_out)
  );
  ALU alu ( // @[XunChunTop.scala 33:21]
    .clock(alu_clock),
    .reset(alu_reset),
    .io_ready_out(alu_io_ready_out),
    .io_valid_out(alu_io_valid_out),
    .io_exeInfo_OperA(alu_io_exeInfo_OperA),
    .io_exeInfo_OperB(alu_io_exeInfo_OperB),
    .io_exeInfo_regwe(alu_io_exeInfo_regwe),
    .io_exeInfo_wAddr(alu_io_exeInfo_wAddr),
    .io_exeInfo_op(alu_io_exeInfo_op),
    .io_exeInfo_AFromReg(alu_io_exeInfo_AFromReg),
    .io_exeInfo_BFromReg(alu_io_exeInfo_BFromReg),
    .io_exeInfo_ARegAddr(alu_io_exeInfo_ARegAddr),
    .io_exeInfo_BRegAddr(alu_io_exeInfo_BRegAddr),
    .io_memInfo_memType(alu_io_memInfo_memType),
    .io_memInfo_memAddr(alu_io_memInfo_memAddr),
    .io_wbInfo_regwe(alu_io_wbInfo_regwe),
    .io_wbInfo_regAddr(alu_io_wbInfo_regAddr),
    .io_wbInfo_wData(alu_io_wbInfo_wData),
    .io_bypassFromExe_regAddr(alu_io_bypassFromExe_regAddr),
    .io_bypassFromExe_regData(alu_io_bypassFromExe_regData),
    .io_bypassFromMem2_regAddr(alu_io_bypassFromMem2_regAddr),
    .io_bypassFromMem2_regData(alu_io_bypassFromMem2_regData),
    .io_isLBandLW(alu_io_isLBandLW),
    .io_wregAddr(alu_io_wregAddr),
    .io_stallFromEXE(alu_io_stallFromEXE),
    .io_addr(alu_io_addr),
    .io_wr(alu_io_wr),
    .io_size(alu_io_size),
    .io_wdata(alu_io_wdata),
    .io_OpA(alu_io_OpA),
    .io_OpB(alu_io_OpB),
    .io_mulans(alu_io_mulans)
  );
  MulModule mulmodule ( // @[XunChunTop.scala 34:27]
    .clock(mulmodule_clock),
    .reset(mulmodule_reset),
    .io_OpA(mulmodule_io_OpA),
    .io_OpB(mulmodule_io_OpB),
    .io_ans(mulmodule_io_ans)
  );
  MEMReg memreg ( // @[XunChunTop.scala 36:24]
    .clock(memreg_clock),
    .reset(memreg_reset),
    .io_memInfo_in_memType(memreg_io_memInfo_in_memType),
    .io_memInfo_in_memAddr(memreg_io_memInfo_in_memAddr),
    .io_memInfo_out_memType(memreg_io_memInfo_out_memType),
    .io_memInfo_out_memAddr(memreg_io_memInfo_out_memAddr),
    .io_wbInfo_in_regwe(memreg_io_wbInfo_in_regwe),
    .io_wbInfo_in_regAddr(memreg_io_wbInfo_in_regAddr),
    .io_wbInfo_in_wData(memreg_io_wbInfo_in_wData),
    .io_wbInfo_out_regwe(memreg_io_wbInfo_out_regwe),
    .io_wbInfo_out_regAddr(memreg_io_wbInfo_out_regAddr),
    .io_wbInfo_out_wData(memreg_io_wbInfo_out_wData),
    .io_valid_in(memreg_io_valid_in)
  );
  MemAccess memaccess ( // @[XunChunTop.scala 37:27]
    .io_memInfo_memType(memaccess_io_memInfo_memType),
    .io_memInfo_memAddr(memaccess_io_memInfo_memAddr),
    .io_wbInfo_in_regwe(memaccess_io_wbInfo_in_regwe),
    .io_wbInfo_in_regAddr(memaccess_io_wbInfo_in_regAddr),
    .io_wbInfo_in_wData(memaccess_io_wbInfo_in_wData),
    .io_wbInfo_out_regwe(memaccess_io_wbInfo_out_regwe),
    .io_wbInfo_out_regAddr(memaccess_io_wbInfo_out_regAddr),
    .io_wbInfo_out_wData(memaccess_io_wbInfo_out_wData),
    .io_rdata(memaccess_io_rdata),
    .io_bypassFromMem1_regAddr(memaccess_io_bypassFromMem1_regAddr),
    .io_bypassFromMem1_regData(memaccess_io_bypassFromMem1_regData),
    .io_bypassFromMem2_regAddr(memaccess_io_bypassFromMem2_regAddr),
    .io_bypassFromMem2_regData(memaccess_io_bypassFromMem2_regData),
    .io_stallFromMEM(memaccess_io_stallFromMEM)
  );
  WBReg wbreg ( // @[XunChunTop.scala 39:23]
    .clock(wbreg_clock),
    .reset(wbreg_reset),
    .io_wbInfo_regwe(wbreg_io_wbInfo_regwe),
    .io_wbInfo_regAddr(wbreg_io_wbInfo_regAddr),
    .io_wbInfo_wData(wbreg_io_wbInfo_wData),
    .io_write_we(wbreg_io_write_we),
    .io_write_addr(wbreg_io_write_addr),
    .io_write_wdata(wbreg_io_write_wdata)
  );
  RegFile regfile ( // @[XunChunTop.scala 41:25]
    .clock(regfile_clock),
    .reset(regfile_reset),
    .io_read_rsAddr(regfile_io_read_rsAddr),
    .io_read_rtAddr(regfile_io_read_rtAddr),
    .io_read_rsData(regfile_io_read_rsData),
    .io_read_rtData(regfile_io_read_rtData),
    .io_write_we(regfile_io_write_we),
    .io_write_addr(regfile_io_write_addr),
    .io_write_wdata(regfile_io_write_wdata)
  );
  assign io_if_addr = control_io_ready_out & ~control_io_stallFromID & ~alu_io_stallFromEXE & ~memaccess_io_stallFromMEM
     & alu_io_ready_out ? pc_io_npc : pc_io_pc; // @[XunChunTop.scala 111:132 XunChunTop.scala 112:20 XunChunTop.scala 114:20]
  assign io_mem_addr = alu_io_addr; // @[XunChunTop.scala 117:17]
  assign io_mem_wr = alu_io_wr; // @[XunChunTop.scala 118:15]
  assign io_mem_size = alu_io_size; // @[XunChunTop.scala 119:17]
  assign io_mem_wdata = alu_io_wdata; // @[XunChunTop.scala 120:18]
  assign pc_clock = clock;
  assign pc_reset = reset;
  assign pc_io_ready_in = idreg_io_ready_out; // @[XunChunTop.scala 45:20]
  assign pc_io_NPC_Type = control_io_NPC_Type; // @[XunChunTop.scala 46:20]
  assign pc_io_pcImm = control_io_NextPC; // @[XunChunTop.scala 47:17]
  assign pc_io_stall = control_io_stallFromID | alu_io_stallFromEXE | memaccess_io_stallFromMEM; // @[XunChunTop.scala 48:66]
  assign idreg_clock = clock;
  assign idreg_reset = reset;
  assign idreg_io_pc_in = pc_io_pc; // @[XunChunTop.scala 51:20]
  assign idreg_io_instr_in = io_if_rdata; // @[XunChunTop.scala 52:23]
  assign idreg_io_ready_in = decode_io_ready_out; // @[XunChunTop.scala 54:23]
  assign idreg_io_valid_in = pc_io_valid_out; // @[XunChunTop.scala 53:23]
  assign idreg_io_stallFromIF = control_io_stallFromID; // @[XunChunTop.scala 55:26]
  assign idreg_io_stallFromEXE = alu_io_stallFromEXE; // @[XunChunTop.scala 56:27]
  assign idreg_io_stallFromMEM = memaccess_io_stallFromMEM; // @[XunChunTop.scala 57:27]
  assign decode_io_instr_in = idreg_io_instr_out; // @[XunChunTop.scala 60:24]
  assign decode_io_pc_in = idreg_io_pc_out; // @[XunChunTop.scala 61:21]
  assign decode_io_ready_in = control_io_ready_out; // @[XunChunTop.scala 62:24]
  assign control_io_controlInfo_regwe = decode_io_controlInfo_regwe; // @[XunChunTop.scala 65:28]
  assign control_io_controlInfo_wAddrSel = decode_io_controlInfo_wAddrSel; // @[XunChunTop.scala 65:28]
  assign control_io_controlInfo_ASel = decode_io_controlInfo_ASel; // @[XunChunTop.scala 65:28]
  assign control_io_controlInfo_BSel = decode_io_controlInfo_BSel; // @[XunChunTop.scala 65:28]
  assign control_io_controlInfo_immExtType = decode_io_controlInfo_immExtType; // @[XunChunTop.scala 65:28]
  assign control_io_controlInfo_op = decode_io_controlInfo_op; // @[XunChunTop.scala 65:28]
  assign control_io_instr = decode_io_instr_out; // @[XunChunTop.scala 66:22]
  assign control_io_pc = decode_io_pc_out; // @[XunChunTop.scala 67:19]
  assign control_io_rsData = regfile_io_read_rsData; // @[XunChunTop.scala 68:23]
  assign control_io_rtData = regfile_io_read_rtData; // @[XunChunTop.scala 69:23]
  assign control_io_bypassFromExe_regAddr = alu_io_bypassFromExe_regAddr; // @[XunChunTop.scala 70:30]
  assign control_io_bypassFromExe_regData = alu_io_bypassFromExe_regData; // @[XunChunTop.scala 70:30]
  assign control_io_bypassFromMem_regAddr = memaccess_io_bypassFromMem1_regAddr; // @[XunChunTop.scala 71:30]
  assign control_io_bypassFromMem_regData = memaccess_io_bypassFromMem1_regData; // @[XunChunTop.scala 71:30]
  assign control_io_ready_in = exereg_io_ready_out; // @[XunChunTop.scala 75:25]
  assign control_io_valid_in = idreg_io_valid_out; // @[XunChunTop.scala 74:25]
  assign control_io_isLBandLW = alu_io_isLBandLW; // @[XunChunTop.scala 72:26]
  assign control_io_wregAddr = alu_io_wregAddr; // @[XunChunTop.scala 73:25]
  assign exereg_clock = clock;
  assign exereg_reset = reset;
  assign exereg_io_exeInfo_in_OperA = control_io_exeInfo_OperA; // @[XunChunTop.scala 78:26]
  assign exereg_io_exeInfo_in_OperB = control_io_exeInfo_OperB; // @[XunChunTop.scala 78:26]
  assign exereg_io_exeInfo_in_regwe = control_io_exeInfo_regwe; // @[XunChunTop.scala 78:26]
  assign exereg_io_exeInfo_in_wAddr = control_io_exeInfo_wAddr; // @[XunChunTop.scala 78:26]
  assign exereg_io_exeInfo_in_op = control_io_exeInfo_op; // @[XunChunTop.scala 78:26]
  assign exereg_io_exeInfo_in_AFromReg = control_io_exeInfo_AFromReg; // @[XunChunTop.scala 78:26]
  assign exereg_io_exeInfo_in_BFromReg = control_io_exeInfo_BFromReg; // @[XunChunTop.scala 78:26]
  assign exereg_io_exeInfo_in_ARegAddr = control_io_exeInfo_ARegAddr; // @[XunChunTop.scala 78:26]
  assign exereg_io_exeInfo_in_BRegAddr = control_io_exeInfo_BRegAddr; // @[XunChunTop.scala 78:26]
  assign exereg_io_valid_in = control_io_valid_out; // @[XunChunTop.scala 79:24]
  assign exereg_io_ready_in = alu_io_ready_out; // @[XunChunTop.scala 80:24]
  assign alu_clock = clock;
  assign alu_reset = reset;
  assign alu_io_exeInfo_OperA = exereg_io_exeInfo_out_OperA; // @[XunChunTop.scala 83:20]
  assign alu_io_exeInfo_OperB = exereg_io_exeInfo_out_OperB; // @[XunChunTop.scala 83:20]
  assign alu_io_exeInfo_regwe = exereg_io_exeInfo_out_regwe; // @[XunChunTop.scala 83:20]
  assign alu_io_exeInfo_wAddr = exereg_io_exeInfo_out_wAddr; // @[XunChunTop.scala 83:20]
  assign alu_io_exeInfo_op = exereg_io_exeInfo_out_op; // @[XunChunTop.scala 83:20]
  assign alu_io_exeInfo_AFromReg = exereg_io_exeInfo_out_AFromReg; // @[XunChunTop.scala 83:20]
  assign alu_io_exeInfo_BFromReg = exereg_io_exeInfo_out_BFromReg; // @[XunChunTop.scala 83:20]
  assign alu_io_exeInfo_ARegAddr = exereg_io_exeInfo_out_ARegAddr; // @[XunChunTop.scala 83:20]
  assign alu_io_exeInfo_BRegAddr = exereg_io_exeInfo_out_BRegAddr; // @[XunChunTop.scala 83:20]
  assign alu_io_bypassFromMem2_regAddr = memaccess_io_bypassFromMem2_regAddr; // @[XunChunTop.scala 84:27]
  assign alu_io_bypassFromMem2_regData = memaccess_io_bypassFromMem2_regData; // @[XunChunTop.scala 84:27]
  assign alu_io_mulans = mulmodule_io_ans; // @[XunChunTop.scala 85:19]
  assign mulmodule_clock = clock;
  assign mulmodule_reset = reset;
  assign mulmodule_io_OpA = alu_io_OpA; // @[XunChunTop.scala 88:22]
  assign mulmodule_io_OpB = alu_io_OpB; // @[XunChunTop.scala 89:22]
  assign memreg_clock = clock;
  assign memreg_reset = reset;
  assign memreg_io_memInfo_in_memType = alu_io_memInfo_memType; // @[XunChunTop.scala 92:26]
  assign memreg_io_memInfo_in_memAddr = alu_io_memInfo_memAddr; // @[XunChunTop.scala 92:26]
  assign memreg_io_wbInfo_in_regwe = alu_io_wbInfo_regwe; // @[XunChunTop.scala 93:25]
  assign memreg_io_wbInfo_in_regAddr = alu_io_wbInfo_regAddr; // @[XunChunTop.scala 93:25]
  assign memreg_io_wbInfo_in_wData = alu_io_wbInfo_wData; // @[XunChunTop.scala 93:25]
  assign memreg_io_valid_in = alu_io_valid_out; // @[XunChunTop.scala 94:24]
  assign memaccess_io_memInfo_memType = memreg_io_memInfo_out_memType; // @[XunChunTop.scala 97:26]
  assign memaccess_io_memInfo_memAddr = memreg_io_memInfo_out_memAddr; // @[XunChunTop.scala 97:26]
  assign memaccess_io_wbInfo_in_regwe = memreg_io_wbInfo_out_regwe; // @[XunChunTop.scala 98:28]
  assign memaccess_io_wbInfo_in_regAddr = memreg_io_wbInfo_out_regAddr; // @[XunChunTop.scala 98:28]
  assign memaccess_io_wbInfo_in_wData = memreg_io_wbInfo_out_wData; // @[XunChunTop.scala 98:28]
  assign memaccess_io_rdata = io_mem_rdata; // @[XunChunTop.scala 99:24]
  assign wbreg_clock = clock;
  assign wbreg_reset = reset;
  assign wbreg_io_wbInfo_regwe = memaccess_io_wbInfo_out_regwe; // @[XunChunTop.scala 102:21]
  assign wbreg_io_wbInfo_regAddr = memaccess_io_wbInfo_out_regAddr; // @[XunChunTop.scala 102:21]
  assign wbreg_io_wbInfo_wData = memaccess_io_wbInfo_out_wData; // @[XunChunTop.scala 102:21]
  assign regfile_clock = clock;
  assign regfile_reset = reset;
  assign regfile_io_read_rsAddr = control_io_rsAddr; // @[XunChunTop.scala 105:28]
  assign regfile_io_read_rtAddr = control_io_rtAddr; // @[XunChunTop.scala 106:28]
  assign regfile_io_write_we = wbreg_io_write_we; // @[XunChunTop.scala 107:22]
  assign regfile_io_write_addr = wbreg_io_write_addr; // @[XunChunTop.scala 107:22]
  assign regfile_io_write_wdata = wbreg_io_write_wdata; // @[XunChunTop.scala 107:22]
endmodule
